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Senior TPU Validation Engineer

Google Mountain View, California, United States

onsite
Posted Aug 4, 2026

**Role & Seniority: ** Senior/Lead SoC Validation Engineer (8+ years) focused on mobile ML accelerator/TPU verification

**Stack/Tools: **

  • C/C++ (test & verification framework development)

  • SoC validation/verification frameworks for pre-/post-silicon flows

  • Emulation-based validation; board-level debug

  • Top 3 Responsibilities:

    • Build a comprehensive verification framework for TPU (ML accelerator) in a Mobile SoC

    • Create test plans and execute pre-silicon emulation and post-silicon validation

    • Perform power/performance measurement and correlate results with pre-silicon targets; support system bring-up/debug with cross-functional teams

  • Must-have Skills:

    • SoC validation experience (8 years)

    • ML accelerator architecture verification/understanding

    • Mobile SoC knowledge: ARM processor, coherent fabric, SMMU

    • Verification framework development in C/C++

  • Nice-to-haves:

    • ML accelerator verification experience

    • Board-level debug, complex system debug

    • Validation on emulation platforms

    • MS/PhD with computer architecture emphasis

  • Location & Work Type: US-based; full-time (Google compensation listed as $163k–$236k USD + ~15% bonus target + equity + benefits). Work type/location specifics not provided beyond “US.”

Full Description

MINIMUM QUALIFICATIONS

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.

  • 8 years of experience in SoC validation.

  • Experience with ML accelerator architecture.

  • Experience with Mobile SoC architecture including ARM processor, coherent fabric, and system memory management unit (SMMU).

  • Experience with test and verification framework development in C/C++.

PREFERRED QUALIFICATIONS

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Prior experience with ML accelerator verification.
  • Experience with board level debug.
  • Experience performing validation on emulation platforms.
  • Experience with complex system debug.

ABOUT THE JOB

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google

[https: //www.google.com/about/careers/applications/benefits/].

RESPONSIBILITIES

  • Collaborate with the team responsible for Silicon validation of TPU (Tensor Processing Unit - Google’s custom ML accelerator) design in mobile System on Chip (SoC).

  • Develop comprehensive verification framework.

  • Develop test plan, perform pre-silicon validation (Emulation) and post-silicon validation.

  • Conduct power, performance measurement and correlation with pre-silicon goal.

  • Collaborate with Software (SW), Architecture (Arch), Design, and Design Verification (DV) teams at different stage of the product development.

SoC validationML accelerator architectureMobile SoC architectureARM processorCoherent fabricSMMUC++CVerification framework developmentBoard level debugEmulation platformsSystem debugPower measurementPerformance measurementSilicon validationmulti-location

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