**Role & seniority: ** Mixed Signal Design Verification Engineer (Experienced Hire), ~3–4+ years (BS: 4+, MS: 3+)

**Stack/tools: ** SystemVerilog, UVM, Verilog; analog behavioral modeling; EDA simulators: Synopsys VCS / Cadence Xcelium / Mentor Questa; scripting: Python or Perl or Tcl; protocols: JTAG, IJTAG, CRI, APB; multi-clock mixed-signal designs; UPF/clock gating (preferred); formal tools (preferred); version control: Git/Perforce (preferred)

**Top 3 responsibilities: **

Create and run functional verification for mixed-signal logic/IPs (incl. analog behavioral models) against design specs
Build verification plans, testbenches, and simulation environments to achieve required microarchitecture/subsystem coverage; implement/execute simulation models for performance/power/timing checks
Debug failures in pre-silicon via root-cause analysis; drive corrective actions; participate in technical reviews and cross-team verification/architecture alignment
Must-have skills:
- Hands-on mixed-signal verification using SV/UVM/Verilog
- Proficiency with at least one major industry simulation tool (VCS/Xcelium/Questa)
- Strong scripting for automation (Python/Perl/Tcl) and debugging (constraint-random, root cause analysis)
Nice-to-haves:
- Low-power verification experience (UPF, clock gating)
- Formal Property Verification tool experience
- Git/Perforce experience and strong collaboration/communication

**Location & work type

Full Description

Job Details

Job Description

The Role and Impact

As a Mixed Signal Design Verification Engineer, you will be instrumental in ensuring Intel's success in delivering innovative and high-quality mixed signal components. By leveraging your technical expertise in verification methodologies, you will validate and enhance the functionality of mixed signal IPs (example PCIE, UCIE, USB4/Type-C PHYs). Your work will directly contribute to Intel's leadership in cutting-edge technology, ensuring the performance, reliability, and efficiency of our products. This role offers a unique opportunity to collaborate with cross-functional teams and contribute to the development of industry-leading solutions.

Key Responsibilities

Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure compliance with design specifications.
Develop comprehensive IP verification plans, test benches, and environments to achieve thorough coverage of mixed signal microarchitecture specifications.
Define and execute simulation models to verify design performance, analyze power and timing, and identify and resolve design bugs.
Conduct root cause analysis and implement corrective measures to address failing tests in the pre silicon environment.
Collaborate with digital and analog architects, RTL developers, and physical design teams to refine and optimize architectural and microarchitectural features.
Lead technical reviews of test plans and validation proofs with design and architecture teams, ensuring meticulous documentation of findings and processes.
Maintain and enhance functional verification methodologies, infrastructure, and tools to align with evolving industry standards and best practices.

Qualifications

Minimum Qualifications

Bachelor's or Master's degree in electronics and communication or electrical engineering, VLSI Engineering, or a related field.
4+ years of experience with a Bachelor's degree, or 3+ years of experience with a Master's degree in ASIC or IP verification, subsystem and function coverage.
Proficiency in mixed signal verification and hands on in IP verification using System Verilog, UVM, and Verilog.
Hands-on experience with industry-standard EDA tools, such as Synopsys VCS, Cadence Xcelium, or Mentor Questa, for simulation and verification.
Strong scripting skills in Python, Perl, or Tcl for automation and efficiency in testbench development.
Familiarity with standard protocols including JTAG, IJTAG, CRI, and APB, as well as multi-clock domain mixed signal designs.
Expertise in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs.

Preferred Qualifications

Experience with low-power design techniques, including UPF and clock gating, to optimize power consumption.
Knowledge of Formal Property Verification tools and version control systems such as Git or Perforce.
Strong collaboration and communication skills with the ability to thrive in a dynamic, multi-disciplinary team environment.

Join us to drive verification excellence at Intel and shape the future of technology. Apply today and be part of our journey to deliver transformative innovations.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Additional Locations

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.