**Role & seniority: ** Tech consultant / solution engineer (customer-facing), ~5–10 years experience

**Stack/tools (stated): **

HDL/verification: UVM, SystemVerilog, Verilog, VHDL, SystemC, SVA (SystemVerilog Assertions)
Coverage: code coverage, functional coverage
Cadence products: Cadence Verification IP or Jasper (plus)
Top 3 responsibilities:
- Lead technical discovery and scope/qualify opportunities for Cadence digital functional logic verification during pre-sales and customer projects
- Plan and execute technical evaluations with customers/internal teams to validate verification solutions; drive adoption and deployment
- Provide expert support, training, and enablement (basic/advanced trainings, demos, ramp-up/accompaniment)
Must-have skills:
- Strong, hands-on hardware design/verification background
- Practical verification experience with UVM + SystemVerilog/Verilog/VHDL/SystemC + SVA
- Knowledge of code coverage and functional coverage concepts/tools
- Clear English communication and ability to work globally with customers and internal teams
- Willingness to travel (passport required)
Nice-to-haves:
- Hands-on experience with Cadence Verification IP and/or Jasper
Location & work type:
- Global/customer-facing; travel required as needed (exact base location not specified)
- Combination of **p

Full Description

Act as a tech consultant to lead and support Cadence digital verification solution for customer projects or pre-sales engagements
Work closely with the sales team to identify, qualify, and scope opportunities for Cadence’s digital functional logic verification solutions.
Understand customer goals and objectives, and plan, execute, and manage key technical evaluations in close collaboration with customers and internal teams.
Proactively engage with existing and prospective customers to ensure successful adoption and deployment of Cadence verification technologies.
Summarize project activities, status, and outcomes, and report effectively to management while sharing knowledge and best practices within the team.
Train, ramp-up and accompany customer project to ensure successful execution and adoption.
Deliver basic and advanced trainings, technical presentations, and product demonstrations as required.
Provide deep technical expertise to address complex customer issues and inquiries that require expert‑level support.

Bachelor’s degree or higher in Computer Science, Electrical Engineering, or a related field, with 5–10 years of relevant industry experience.
5–10 years of hands‑on experience and strong expertise in hardware design and/or verification methodologies.
Solid hands‑on verification experience using UVM, SystemVerilog, Verilog, VHDL, SystemC, and SystemVerilog Assertions (SVA).
Hands‑on experience with Cadence Verification IP or Jasper is a strong plus.
Good understanding of code coverage and functional coverage concepts, tools, and technologies.
Strong communication skills in English, with the ability and motivation to work in a global, customer‑facing environment with customers and internal business unit teams.
Valid passport with no travel restrictions; willingness to travel as required.