**Role & seniority: ** ASIC/Connectivity RF-analog engineering role; implementation of system architectures/interfaces/logic; likely mid-level (no explicit seniority stated).

**Stack/tools: ** RTL design; ASIC front-end; scripting Python or Perl; unit/integrated testbenches; synthesis and gate-level simulation; timing closure across chip; wireless protocols knowledge (Wireless LAN, Bluetooth); RF transceiver domain.

**Top 3 responsibilities: **

Develop/implement connectivity RF/analog system architectures, interfaces, and logic for multi-function mobile platforms.
Create/maintain unit-level and integrated-level test benches and perform simulation/synthesis for modules.
Support gate-level simulation and chip-level timing (timing analysis/closure).
Must-have skills:
- RTL design experience.
- ASIC front-end experience.
- Scripting proficiency (Perl or Python).
- Knowledge applying wireless LAN/Bluetooth and RF transceiver concepts.
Nice-to-haves:
- Deeper RF/analog connectivity experience; specifics not listed beyond wireless/RF domain alignment.
- Strong experience with integrated verification and timing sign-off activities (implied).
Location & work type: Not specified in the provided text; US compensation range listed ($113,000–$169,600). Work type/location details are missing.

Full Description

Company

Qualcomm Atheros, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm-Atheros is a leading provider of wireless and wired technologies for the mobile, networking, computing and consumer electronics markets. We're focused on inventing technologies that connect and empower people in ways that are elegant and accessible to all. Qualcomm Atheros' teams deliver cutting-edge products across every established wireless standard/protocol.

We are currently seeking candidates for positions involving the implementation of optimum system architectures, interfaces and logics for connectivity RF/Analog system. Successful candidates will be responsible for participating in development of leading-edge ASICs for multi-function mobile platforms. Candidates will work with engineers or develop unit-level and integrated-level test benches. Candidate will assist in synthesis and gate-level simulation tasks related to your module and will assist with timing of the entire chip. Candidate will leverage knowledge of wireless LAN, Bluetooth, and RF transceiver.

Ideal candidate will have

*RTL Design *ASIC front-end experience *Scripting Languages knowledge (e.g. Perl or Python)

Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field.
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Pay range and Other Compensation & Benefits

$113,000.00 - $169,600.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.

ASIC Design Verification Engineer