Role & seniority: Functional Verification Engineer; Mid-Senior level (≥5 years in verification of complex SoC/IP); Master’s degree required.

Stack/tools: SystemVerilog/UVM, SystemC/C++, C; Stimulus/Checkers/Assertions/Trackers/Coverage; constrained random, functional coverage; UPF/Formal Verification; HW-SW co-verification; scripting (Bash/Perl/Python); verification management tools; CI/CD tooling.

Top 3 responsibilities

Develop and maintain verification environments across SystemVerilog/UVM/SystemC/C++ components (stimulus, checkers, assertions, trackers, coverage).
Execute verification plans (design bring-up, DV environment bring-up, regressions) and debug test failures; create/exe cu test cases in embedded C and SV.
Collaborate cross-functionally to achieve verification closure: coverage analysis, bug tracking, regression testing, and process/methodology improvements.

Must-have skills: Master’s degree; ≥5 years in verification of complex SoC/IP; strong experience in SystemVerilog/UVM and SystemC/C++; constrained random, functional coverage, design debug; formal verification (UPF); HW-SW co-verification and simulation; scripting (Bash/Perl/Python); verification tools; robust debugging and English proficiency.
Nice-to-haves: Firmware-based verification experience; metrics-driven verification; knowledge of NOC/IPS or peripherals (PCIe, DDR, HBM).
Location & work type: Rome, Italy; hybrid work environment with flexible schedule.

Full Description

The Role

As a Functional Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.

Key Responsibilities

Reading and analysing the system requirements and architecture requirement documents.

Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.

Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.

Using the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, …).

Create and execute testcases to verify the functionality, performance, and robustness in embedded C and SV.

Identify, isolate, and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams.

Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.

Participation to verification methodology improvements.

Qualifications

Master Degree in relevant field. Min 5 years of experience in relevant field of Verification of complex SoC or IP Experience in SystemVerilog/UVM and SystemC/C++ Experience in Constrained random, Functional Coverage development, design debug. Experience in Formal Verification, UPF. Experience in HW-SW co-verification and simulation. Some previous experience in Firmware based verification is a good to have. Some knowledge of scripting languages like Bash/Perl/Python. Use of verification management tools. Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues. Good level of English, both written and spoken is mandatory.

Experience In The Following Are a Plus

Experience in Firmware-based verification. Knowledge in metrics-driven verification. Insights of NOC and other Ips or standard peripherals like PCIe, DDR, HBM …

Soft Skills

Team player, able to work with multiple cultures both on site and remotely. Autonomous and flexible is mandatory.

What do we offer?

Join an innovative team and experience company growth. We believe in investing in our employees and providing them with the opportunities they need to grow and develop their careers. Enjoy a hybrid work environment. We also offer flexible schedule. We offer a remuneration that values your experience. The position will have the base in Rome.