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Infineon Technologies • Bengaluru, Karnataka, India
Role & seniority
Stack/tools
Analog/mixed-signal blocks: power management, clock circuits, data converters; loop analysis a plus
HDL/HVL: Verilog, Verilog-AMS, SystemVerilog/UVM; Wreal, SV-RNM
Verification: AMS verification for SoC/IPs; behavioral modeling
Tools: Cadence Xcelium + Spectre; Synopsys XA-VCS; Mentor Eldo ADMS
Scripting/Automation: Perl, Python, shell
Top 3 responsibilities
Plan and execute AMS verification for SoC/IPs; develop test plans aligned to product specs
Debug test cases and propose new verification scenarios; drive process improvements in methodologies
Lead project scope/schedule/effort decisions; mentor junior engineers and manage multi-site collaboration
Must-have skills
Bachelors + 5+ years of relevant experience
Deep understanding of analog/mixed-signal building blocks and functional specs
Proficiency in Verilog/Verilog-AMS, SV/UVM; Wreal as applicable
Experience with Cadence/Synopsys/Mentor toolchains; scripting in Perl/Python/Shell
Proven ability to drive projects and debug independently; results- and schedule-oriented
Nice-to-haves
Experience with loop analysis; Cadence/Xcelium, Spectre; XA-VCS, Eldo ADMS
Prior exposure to AMS methodologies and full-system verification in multi-site environments
Location & work type
Location: not specified
Work type: not spe
Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment.
Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full
Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort – coming up with alternative verification plans, Mentoring Junior engineer – Partial Ability to drive MSV project independently Drive enhancements in known methodologies
Bachelors with 5+ years of experience
Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage
HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage
Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS
Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently
#WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?
We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.