Full Description

ASIC Verification Engineer

Location: Gliwice / Kraków (hybrid) | Remote across Poland & EU (senior-level only)

Employment Type: B2B cooperation or Employment contract

Company: Vtool

About Vtool Vtool is a global semiconductor engineering company specializing in ASIC design services, advanced functional verification, and EDA tools. Founded in Israel, Vtool operates engineering centers across Europe and the Middle East, supporting leading semiconductor companies worldwide. At the core of Vtool’s technology portfolio is Cogita-PRO, an AI-driven analytics and debug platform that dramatically accelerates verification cycles by transforming massive simulation and regression data into actionable insights. In addition to its EDA tools, Vtool provides end-to-end ASIC design and verification services, delivering high-quality silicon for complex SoC and ASIC projects.

Role Overview As an ASIC Verification Engineer, you will contribute to the development and execution of advanced functional verification environments for complex ASIC and SoC designs. You will work on technically challenging projects for global semiconductor leaders, collaborating closely with design, architecture, and verification methodology teams. This position offers hybrid work from Gliwice or Kraków. For senior-level engineers, fully remote work is available across Poland and the European Union, provided the candidate holds legal eligibility to work in the EU.

Key Responsibilities Develop, maintain, and optimize SystemVerilog / UVM-based verification environments Define and execute verification plans, test strategies, and coverage models Implement constrained-random testbenches and functional coverage Analyze regressions, debug complex failures, and perform root-cause analysis Collaborate with RTL designers, architects, and system engineers to ensure design correctness Drive verification methodology improvements, automation, and best practices

For senior engineers: Lead verification activities. Own verification architecture for major blocks or subsystems. Mentor junior engineers

Required Qualifications BSc or MSc in Electrical Engineering, Computer Engineering, Computer Science, or related field Strong hands-on experience with SystemVerilog Solid knowledge of UVM (or equivalent verification methodologies) Practical experience in functional verification of ASIC / SoC designs Good understanding of digital design concepts and RTL design flows Experience working in Linux environments Scripting skills in Python, Tcl, or Bash Strong analytical, debugging, and problem-solving skills Fluent English (written and spoken)

Nice to Have Experience in full-chip or system-level SoC verification Knowledge of AMBA protocols (AXI, AHB, APB) Familiarity with PCIe, USB, UCIe, Ethernet, DDR, RISC-V, or ARM-based architectures Experience with emulation, FPGA prototyping, or hardware acceleration platforms Background in coverage-driven verification and regression infrastructure