🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Cookies & analytics consent
We serve candidates globally, so we only activate Google Tag Manager and other analytics after you opt in. This keeps us aligned with GDPR/UK DPA, ePrivacy, LGPD, and similar rules. Essential features still run without analytics cookies.
Read how we use data in our Privacy Policy and Terms of Service.
🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Cadence Design Systems • Shanghai, Shanghai, China
Salary: 100 Best Compa
Role & seniority: Digital design engineer (PhD or MS + 3–5 years of experience) at Cadence; individual contributor with emphasis on timing and library characterization.
Stack/tools: Linux; scripting (proficient); STA/EXT timing concepts; P&R timing; cell/transition-level simulation and library characterization (plus related EDA workflows).
Perform timing analysis and verification (STA/EXT) for digital designs.
Conduct cell/transition-level simulations and library characterization to support design flows.
Collaborate with team on timing-driven design work and contribute to reliable, scalable EDA processes.
Familiarity with Linux and proficient scripting
PhD or MS degree with 3–5 years of digital design experience
Knowledge of STA/EXT timing concepts and P&R timing
Strong written and verbal communication; reliable, patient, and responsible
Nice-to-haves: Experience in cell/transition-level simulation or library characterization
Location & work type: Not specified by the posting (location/work type unavailable)
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 1. The candidate should be familiar with Linux system, and proficient scripting skills; 2. The candidate should have PhD, or Master degree with 3~5 years of digital design experience. 3. The candidate should be familiar with STA/EXT knowledge & P&R timing, a cell/transition level simulation or library characterization experience is a plus. 4. Good team player with strong written and verbal communication skills, and with good patience & responsibility. We’re doing work that matters. Help us solve what others can’t. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.