Full Description

Develop and implement robust test strategies, plans, and ATE programs for HBM-DRAM devices. Drive silicon validation, characterization, and yield improvement initiatives. Design and debug test hardware, including schematic capture and PCB layout. Collaborate cross-functionally to ensure seamless integration of test solutions into production. Support high-volume manufacturing and troubleshoot complex test issues. Education: Bachelor's or Master's degree in Electrical or Computer Engineering. Experience: 7+ years in Test Engineering with proven expertise in ATE platforms. Strong programming skills for writing and debugging ATE test programs and test-related hardware development Proficiency with Advantest V93K or other logic device ATE testers. Programming in C/C++ and/or Java. Solid understanding of CMOS SoC testing; exceptional experience with digital, analog, and MXS test programming and debugging Familiarity with testing IP blocks (PLL, eFuse, DDR). Expertise in test strategy development, test plan definition. Expertise in DFT pattern implementation (ATPG SCAN, TDF, MemBIST, BSACAN, JTAG/IEEE1500 and functional patterns). Hands-on experience with ATE architecture, test hardware design and debugging, schematic capture, and PCB layout. Hands-on experience with ATE test vector conversion tools like VTRAN and proficiency in debugging issues during development or high volume production. Semiconductor manufacturing processes. Knowledge of accurate and effective use of lab test equipment (i.e., oscilloscope, logic analyzer, etc.). Data analysis tools (e.g., JMP) for characterization and yield reporting. Soft Skills: Excellent communication, problem-solving, and collaboration abilities.