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UST • Bengaluru, Karnataka, India
Role & seniority: Technical Lead II - VLSI; Mid–Senior level FPGA/verification leadership with 10+ years in the field.
Stack / tools: FPGA/ASIC RTL principles; SystemVerilog and UVM; Linux; QuestaSim, Synopsys VCS, Haps; high-speed I/O protocols (PCIe, I2C, SPI); lab debugging tools (logic analyzer, oscilloscope, JTAG).
Create and maintain test benches using UVM/SystemVerilog; write and debug test cases for functionality, performance, and corner cases.
Identify, debug, and resolve issues; collaborate with design engineers; contribute to verification strategy and design reviews.
Stay current with verification methodologies and tools; contribute to overall verification quality.
Deep FPGA/ASIC RTL design principles and architectures; SystemVerilog/UVM proficiency; Linux experience.
Experience with QuestaSim, VCS, or similar tools; high-speed I/O protocols knowledge; lab debugging capability.
Strong debugging, problem-solving, and collaboration skills.
Hardware validation or embedded test automation experience.
Scripting skills (Python, Perl).
Location & work type: Full-time role; location not specified in provided text.
Role Description
UST Job Title: Technical Lead II - VLSI
Who We Are
At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at UST.com.
The Opportunity
We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team, working on state of the art technologies. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products.
Key Responsibilities
Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, System Verilog, RTL). Write and debug test cases to verify functionality, performance, and corner cases. Identify and debug issues, working closely with design engineers to resolve them. Participate in design reviews and contribute to the overall verification strategy. Stay up-to-date with the latest verification methodologies and tools.
Required Skills
Strong understanding of FPGA, ASIC, RTL design principles and architectures. Proficiency in System Verilog and UVM verification methodology. Experience with Linux operating system. Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps). Experience with high-speed I/O design and protocols. Knowledge of PCIe, I2C, SPI, etc. Hands on experience with lab debugging tools including logic analyzer, oscilloscope, and JTAG. Excellent debugging and problem-solving skills. Strong communication and collaboration skills.
Desired Skills
Experience in hardware validation or embedded test automation Experience with scripting languages (e.g., Python, Perl).
Qualification
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in FPGA design or verification. Familiarity with hardware description languages (e.g., VHDL, Verilog).
Humility
We listen, learn, and help selflessly in our interactions
Humanity
We use business to improve lives
Integrity
We honor commitments and act responsibly in relationships
Equal Employment Opportunity Statement
UST is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Skills
FPGA,RTL,System Verilog,Uvm
Seniority level Mid-Senior level Employment type Full-time Job function Engineering and Information Technology Industries IT Services and IT Consulting