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Ciena • Ottawa, Ontario, Canada
Salary: C$103,700 - C$165,700 / year
Role & seniority: Senior FPGA/ASIC verification engineer (8+ years)
Stack/tools: SystemVerilog, UVM, directed/constrained-random testbench development; Linux/Unix; Mentor Graphics Questa; Synopsys VCS; PCIe, I2C, SPI; OTN; Ethernet interfaces (CAUI, XLAUI, XAUI, XFI)
Establish verification methodology, architecture, and infrastructure; define test priorities and coverage targets; create verification plans aligned to milestones
Develop and execute directed and constrained-random testcases; triage regressions; generate detailed defect reports and drive resolution
Mentor junior verification engineers; provide schedule estimates; communicate with project stakeholders
8+ years FPGA/ASIC verification experience
Hands-on testbench development with SystemVerilog and UVM
Strong debugging/problem-solving; Linux/Unix proficiency
Experience with Mentor Questa and Synopsys VCS
Familiarity with PCIe, I2C, SPI; solid understanding of OTNs and Ethernet interfaces (CAUI, XLAUI, XAUI, XFI)
Strong communication and cross-team collaboration
Experience coaching less-experienced engineers
Highly organized, detail-oriented approach; creative problem-solving in methodology
Location & work type: Primary location listed (Canada); full-time role; supportive, flexible work environment with emphasis on growth and belonging
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. Join a highly skilled team advancing the verification of industry‑leading Field‑Programmable Gate Array (FPGA) technologies that power high‑speed, next‑generation networks. This role drives chip‑level verification excellence, influences methodology and architecture, and ensures the delivery of robust, high‑quality designs that strengthen Ciena’s position as a global leader in adaptive networking. How you will make an impact: Establish verification methodology, architecture, and infrastructure, including models, generators, monitors, and scoreboards Define test priorities and coverage targets in close partnership with design teams Develop comprehensive verification plans aligned to program milestones Create and execute directed and constrained‑random testcases using SystemVerilog and the Universal Verification Methodology (UVM) Triage regressions, generate detailed reports, and drive resolution of defects Mentor junior verification engineers on verification strategies and best practices Provide accurate schedule estimates and maintain clear communication with project stakeholders The must haves: Bachelor’s degree in Engineering (or equivalent experience) Minimum 8 years of FPGA or Application‑Specific Integrated Circuit (ASIC) verification experience Hands‑on expertise developing testbench environments using SystemVerilog and the Universal Verification Methodology (UVM) Strong debugging and problem‑solving skills Experience with both directed and constrained‑random stimulus generation Working knowledge of Linux/Unix and PC operating environments Experience with Mentor Graphics Questa and Synopsys VCS verification tools Familiarity with industry‑standard interfaces such as Peripheral Component Interconnect Express (PCIe), Inter‑Integrated Circuit (I²C), Serial Peripheral Interface (SPI), and a solid understanding of Optical Transport Network (OTN) as well as Ethernet packet structures and interfaces including CAUI, XLAUI, XAUI, and XFI Nice to haves: Strong communication skills with the ability to convey complex technical concepts clearly Demonstrated ability to collaborate effectively across multidisciplinary teams Experience guiding or coaching less‑experienced engineers Highly organized, detail‑oriented approach to project execution Creativity in problem‑solving and methodology development Pay Range: The annual pay range for this position is $103,700 - $165,700 CAD. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Join our Talent Community and get early job alerts, personalized career tips, and insider insights. Discover how Ciena's unique blend of deep humanity and relentless innovation creates an exceptional workplace culture. Explore CienaLife.