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NVIDIA • Yokneam Ilit, North District, Israel
Role & seniority: Test Architect / Senior Electronic Engineer, System Product Engineering (Networking systems) at NVIDIA.
Stack/tools: HW, SW, FW; design-for-testability (DFT); production test fixtures, cables/harnesses; QA/ V&V methods; big-data analysis, ML/statistical tooling for quality monitoring; collaboration with contract manufacturers and suppliers.
Define and optimize product testing architectures across HW, SW, FW, mechanics, and production fixtures; ensure maximum test coverage and create testing specifications and production test flows.
Lead DFT risk assessment, drive mitigations, and influence product design for testability during pre-design to design phases.
Support production ramp-up and scalability, manage ECR/ECO implications, and validate test performance and stability.
BSc/MSc in Electrical Engineering; 5+ years as DFT engineer at chip/system level, board design engineer, or system architect.
Strong integration and self-task management; deep electronic knowledge; experience with contract manufacturers and suppliers; multitasking and organized with quick learning.
Experience analyzing manufacturing data with machine learning or AI-based quality tools; leadership in multi-functional project delivery; experience with failure analysis and root-cause investigation.
Location & work type: Not specified in the provided information.
Responsibilities
Development and deployment of automatic testers for NVIDIA’s network business units (Computing network adapters and High-speed switch systems) including hardware and software Analyzing and monitoring the manufacturing data and find / prevent quality issues based on big data using Machine learning, statistical tools, and AI (artificial intelligence) Leading smooth production and capacity enlargement Failure analysis of return material from customers to understand the reason of failures. Validate the test performance and stability using QA (V&V – validation and verification) methods
The teams are involving and part of the full product lifecycle from architecture definition trough development till the product will be EOL (end of life). As part of the effort mentioned above, we are looking for an Electronic Engineer to join the System Design Testing Architecture team and lead Systems HW testability definition for NVIDIA’s Networking systems.
What You’ll Be Doing
Leading optimal products testing definitions includes: HW, SW, FW, Mechanical fixtures, and cables/harnesses for customized production testing set ups. Making pitches in front of large audience a new product testing architecture, DFT and testing method while providing justifications for the testing concept. Responsible for product testing maximum coverage, Testing specification documents and production test flow process for each system Working with Company’s engineering team during the developing process of the product from pre-design trough the design and influence on the product design from DFT – design for testability aspects. Supporting production ramp up and scalability, lead and fast responding time for ECR/ECO implications. Examine New Technologies, testing capabilities and their implementation for the next generation products Ensure testing set ups and coverage are met the DFT requirements and timetable Lead DFT Risk assessment and drive mitigations to reduce the risks.
What We Need To See
BSc, MSc Electrical Engineering Integration capabilities of self-task management, vast electronic knowledge, production and testing process knowhow. Background in working with contract manufacturers and suppliers Minimum 5 years of experience as a DFT engineer at chip/system level, as Board Design engineer or as system architect Management and follow up till completion of multi-functional and personal tasks.
Personal skills: proactive and self-instruction, good interpersonal relationship, multitasking, well organized and a quick learner.
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