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ACL Digital • Hyderabad, Telangana, India
Role & seniority: Senior Physical Verification Engineer
Location & work type: Hyderabad, India | On-site; Immediate to 15 days notice
Experience & education: 3–4 years; B.Tech/M.Tech in Electronics, Electrical Engineering, or VLSI
Expert: Mentor Graphics Calibre (nmDRC, nmLVS, PERC)
Proficient: Synopsys ICV (In-Design/Sign-off) or Cadence Pegasus
PnR interaction: Innovus or ICC2/Fusion Compiler (understanding physical gaps)
Foundry knowledge: TSMC/Samsung/Intel Foundry Design Manuals
Parasitics & layout: CMOS layout, PEX, dummy fill, slotting, guard rings
Scripting: Tcl, Perl, Python; Calibre SVRF/TVF code familiarity is a plus
Execute and debug DRC, LVS, and ERC sign-off at block and full-chip levels
Identify/resolve complex layout issues (shorts, antenna violations, density)
Drive design convergence and tape-out readiness with Physical Design/Layout teams
Expert Calibre nmDRC/nmLVS and PERC usage
Proficiency in ICV or Cadence/Genus sign-off workflows
Strong understanding of foundry rules and parasitic extraction
Tcl/Python/Perl scripting for automation
Problem-solving for hard-to-find shorts/opens in large SoC databases
Calibre SVRF/TVF scripting capability
Experience with 7nm/5nm nodes or advanced process nodes
Experience communicating sign-off status and risks to stakeholders
Senior Physical Verification Engineer
Location: Hyderabad, India
Experience: 3–4 Years
Notice Period: Immediate to 15 Days (Mandatory)
Education: B.Tech/M.Tech in Electronics, Electrical Engineering, or VLSI.
Role Objective As a Physical Verification (PV) Engineer, you will be responsible for ensuring the physical integrity and manufacturability of complex SoCs and high-performance digital blocks. You will work on cutting-edge process nodes (7nm, 5nm, and below), driving sign-off convergence through rigorous DRC/LVS analysis and cross-functional collaboration.
Key Responsibilities
Role: Execute and debug DRC, LVS, and ERC sign-off at the block and full-chip levels using industry-standard tools like Calibre or ICV.
Core Tasks: Identify and resolve complex layout issues, including connectivity shorts, antenna violations, and density requirements on advanced process nodes (7nm/5nm).
Collaboration: Work closely with Physical Design and Layout teams to drive design convergence and ensure tape-out readiness.
Technical Skills Required
Expertise: Mentor Graphics Calibre (nmDRC, nmLVS, PERC).
Proficiency: Synopsys ICV (In-Design / Sign-off) or Cadence Pegasus.
PnR Interaction: Familiarity with Innovus or ICC2/Fusion Compiler to understand physical implementation gaps.
Scripting: Proficiency in Tcl, Perl, or Python for automation. Ability to write or modify Calibre SVRF/TVF code is a major plus.
Soft Skills & Qualifications
Immediate Availability: Must be able to join within 0–15 days.
Problem Solving: Proven ability to debug "hard-to-find" shorts and opens in massive SoC databases.
Communication: Strong verbal and written skills for reporting sign-off status and risks to stakeholders.