Full Description

About Us

• Headquartered in Ottawa, BTA Design serves the electronic design community in Canada and beyond, specializing in ASIC and FPGA design and verification, and embedded software development services. We augment and enhance our clients’ teams and accelerate the development of complete designs.

We’re adaptable and efficient, with a brilliant staff at our core. We aim to be the best at what we do.

Our success continues to fuel growth. We are currently searching for a number of key technical resources, including a Senior ASIC Verification Engineer with expertise in UVM and PCIe.

Position Overview In this role, you will work with a highly experienced team of verification professionals performing constrained-random, functional-coverage–based verification using SystemVerilog and UVM. You will work from spec to coverage-closed, verified, and debugged designs, developing environments, integrating and leveraging 3rd-party VIP, and ensuring robust verification of complex, high-speed interface and networking blocks. You will verify blocks, subsystems, or top-level functionality within large and extremely complex networking-centric or HPC/AI SoCs built on advanced technology nodes down to 3nm FinFET. You will collaborate closely with strong, deeply experienced design leads in world-class ASIC environments across BTA’s client base.

Key Responsibilities

• Join a team verifying blocks, subsystems, or entire chips—with an emphasis on high-speed interfaces and networking IP
• Support the verification lead on project planning and management of front-end development activities
• Develop test and coverage plans, as well as verification environment architectures, using SystemVerilog and UVM
• Capture test coverage points and write targeted and constrained-random test cases
• Employ constrained-random verification approaches and assertion-based verification where appropriate
• Support silicon and lab bring-up with directed tests, especially for high-speed interface validation
• Perform and analyze both code and functional coverage to drive closure

Key Qualifications

• 8+ years of experience in ASIC verification
• Deep expertise in Verilog, SystemVerilog, and scripting languages
• Proven experience with the responsibilities listed above
• Significant experience with OVM/UVM methodologies
• Experience developing test and coverage plans from scratch
• Experience architecting and developing multiple SV/UVM verification environments, both from scratch and through re-use, would be ideal
• Strong expertise in constrained-random verification techniques, assertions, and functional coverage