Full Description

We are seeking an experienced ASIC Verification Engineer to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.

Responsibilities

1. Verification Planning and Execution:

   • • Develop and execute comprehensive verification plans.
   • • Close verification with coverage closure, ensuring high-quality results.
   • • Apply standard ASIC verification techniques, including test planning,
     • testbench creation, code and functional coverage, directed and random
     • stimulus generation, and assertions.

2. Testbench Development:

   • • Create and enhance testbenches using SystemVerilog (OVM/UVM) or other
     • standard testbench languages.
   • • Implement reusable Verification IP (VIP) components.
   • • Collaborate with third-party VIP providers.

3. Methodology and Flows:

   • • Demonstrate a solid understanding of ASIC design and verification
     • methodologies.
   • • Apply object-oriented programming principles effectively.
   • • Implement constraint random verification methodology.

4. Technical Skills:

   • • Proficiency in SystemVerilog (OVM/UVM) and other relevant languages
     • (C/C++, Perl, Tcl, Python, Verilog PLI).
   • • Familiarity with industry standards (e.g., I2C/SPI).
   • • Experience with low-power verification using UPF (Unified Power Format) is
     • a plus.
   • • Knowledge of formal verification techniques is advantageous.

5. Collaboration and Communication:

   • • Work effectively with internal teams and external customers.