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Staff Verification Engineer

onsemi Bangalore, Karnataka, India

onsitefull-time
Posted Feb 27, 2026

Role & seniority: Experienced ASIC Verification Engineer (seniority: experienced)

Stack / tools: SystemVerilog (OVM/UVM), testbench development; languages: C/C++, Perl, Tcl, Python, Verilog PLI; Verification IP (VIP); UPF (Power intent); I2C/SPI standards; formal verification (advantage)

Top 3 responsibilities

  1. Verification planning and execution: develop/execute verification plans, achieve coverage closure, apply standard ASIC verification techniques

  2. Testbench development: create/enhance SystemVerilog testbenches, implement reusable VIP components, collaborate with third-party VIPs

  3. Methodology and flows: apply ASIC design/verification methodologies, object-oriented practices, constraint-random verification

  • Must-have skills: proficiency in SystemVerilog (OVM/UVM); strong testbench/test planning experience; exposure to coverage metrics, directed/random stimuli, assertions; programming in C/C++, Python, Tcl; familiarity with I2C/SPI; collaboration and communication abilities

  • Nice-to-haves: UPF for low-power verification; formal verification techniques

  • Location & work type: location not specified; work type not specified

Full Description

We are seeking an experienced ASIC Verification Engineer to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.

Responsibilities

  1. Verification Planning and Execution:

      • Develop and execute comprehensive verification plans.
      • Close verification with coverage closure, ensuring high-quality results.
      • Apply standard ASIC verification techniques, including test planning,
      • testbench creation, code and functional coverage, directed and random
      • stimulus generation, and assertions.
  2. Testbench Development:

      • Create and enhance testbenches using SystemVerilog (OVM/UVM) or other
      • standard testbench languages.
      • Implement reusable Verification IP (VIP) components.
      • Collaborate with third-party VIP providers.
  3. Methodology and Flows:

      • Demonstrate a solid understanding of ASIC design and verification
      • methodologies.
      • Apply object-oriented programming principles effectively.
      • Implement constraint random verification methodology.
  4. Technical Skills:

      • Proficiency in SystemVerilog (OVM/UVM) and other relevant languages
      • (C/C++, Perl, Tcl, Python, Verilog PLI).
      • Familiarity with industry standards (e.g., I2C/SPI).
      • Experience with low-power verification using UPF (Unified Power Format) is
      • a plus.
      • Knowledge of formal verification techniques is advantageous.
  5. Collaboration and Communication:

      • Work effectively with internal teams and external customers.
      • Strong written and verbal communication skills.
      • Initiative, analytical problem-solving abilities, and adaptability within
      • a diverse team environment.

#LI-RG1

onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

More details about our company benefits can be found here

https: //www.onsemi.com/careers/career-benefits

[https: //www.onsemi.com/careers/career-benefits]

We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

SystemVerilogOVMUVMC/C++PerlTclPythonVerilog PLIASIC VerificationTestbench CreationCoverage ClosureConstraint Random VerificationUPFI2CSPIFormal Verificationmulti-location

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