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Staff Verification Engineer

onsemi Bangalore, Karnataka, India

onsitefull-time
Posted Feb 27, 2026

Role & seniority: ASIC Verification Engineer (experienced/ senior level)

Stack/tools: SystemVerilog (OVM/UVM) testbenches; testbench languages; Verification IP (VIP); C/C++, Perl, Tcl, Python, Verilog PLI; industry interfaces (I2C/SPI); UPF (low-power verification) is a plus; formal verification beneficial; collaboration with third-party VIPs

Top 3 responsibilities

  • Develop and execute verification plans; drive coverage closure and high-quality results

  • Build/enhance testbenches; implement reusable VIP components; coordinate with third-party VIP providers

  • Apply ASIC verification methodologies and flows; constraint random verification; apply OO concepts

Must-have skills

  • Proficiency in SystemVerilog (OVM/UVM)

  • Testbench development and verification planning with coverage metrics

  • Experience with I2C/SPI and related standards

  • Programming/scripting: C/C++, Python, Tcl, Perl; Verilog PLI

  • Strong collaboration and communication abilities

Nice-to-haves

  • Low-power verification experience using UPF

  • Formal verification techniques

  • Experience with external customers and cross-team collaboration

Location & work type: Location and work-type not specified in posting; additional details to follow from recruiter.

Full Description

We are seeking an experienced ASIC Verification Engineer to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.

Responsibilities

  1. Verification Planning and Execution:

      • Develop and execute comprehensive verification plans.
      • Close verification with coverage closure, ensuring high-quality results.
      • Apply standard ASIC verification techniques, including test planning,
      • testbench creation, code and functional coverage, directed and random
      • stimulus generation, and assertions.
  2. Testbench Development:

      • Create and enhance testbenches using SystemVerilog (OVM/UVM) or other
      • standard testbench languages.
      • Implement reusable Verification IP (VIP) components.
      • Collaborate with third-party VIP providers.
  3. Methodology and Flows:

      • Demonstrate a solid understanding of ASIC design and verification
      • methodologies.
      • Apply object-oriented programming principles effectively.
      • Implement constraint random verification methodology.
  4. Technical Skills:

      • Proficiency in SystemVerilog (OVM/UVM) and other relevant languages
      • (C/C++, Perl, Tcl, Python, Verilog PLI).
      • Familiarity with industry standards (e.g., I2C/SPI).
      • Experience with low-power verification using UPF (Unified Power Format) is
      • a plus.
      • Knowledge of formal verification techniques is advantageous.
  5. Collaboration and Communication:

      • Work effectively with internal teams and external customers.
      • Strong written and verbal communication skills.
      • Initiative, analytical problem-solving abilities, and adaptability within
      • a diverse team environment.

#LI-RG1

onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

More details about our company benefits can be found here

https: //www.onsemi.com/careers/career-benefits

[https: //www.onsemi.com/careers/career-benefits]

We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

SystemVerilogOVMUVMC/C++PerlTclPythonVerilog PLIUPFI2CSPIConstraint Random VerificationObject-Oriented ProgrammingFormal Verificationmulti-location

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