
Staff Verification Engineer
onsemi • Bangalore, Karnataka, India
Role & seniority
- Experienced ASIC Verification Engineer
Stack / tools
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SystemVerilog (OVM/UVM), testbench development
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Verification IP (VIP) components, third-party VIP collaboration
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Languages: C/C++, Perl, Tcl, Python, Verilog PLI
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Methodologies: constraint random verification, coverage-driven verification
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Industry standards: I2C, SPI; low-power verification with UPF (plus); formal verification (nice-to-have)
Top 3 responsibilities
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Develop and execute comprehensive verification plans and achieve coverage closure
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Create/enhance testbenches (SystemVerilog, OVM/UVM), implement reusable VIPs, collaborate with external VIP providers
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Apply ASIC design/verification methodologies, object-oriented practices, and constraint-random verification
Must-have skills
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Proficiency in SystemVerilog (OVM/UVM) and associated languages (C/C++, Perl, Tcl, Python)
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Experience with testbench development, coverage collection, and assertion-based techniques
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Familiarity with I2C/SPI; ability to work with verification plans and coverage closure
Nice-to-haves
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UPF-based low-power verification experience
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Formal verification knowledge
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Strong collaboration, communication, and problem-solving in a diverse team
Location & work type
- Location and work-type not specified in the posting; please refer to the official listing for details
Full Description
We are seeking an experienced ASIC Verification Engineer to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.
Responsibilities
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Verification Planning and Execution:
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- Develop and execute comprehensive verification plans.
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- Close verification with coverage closure, ensuring high-quality results.
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- Apply standard ASIC verification techniques, including test planning,
- testbench creation, code and functional coverage, directed and random
- stimulus generation, and assertions.
-
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Testbench Development:
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- Create and enhance testbenches using SystemVerilog (OVM/UVM) or other
- standard testbench languages.
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- Implement reusable Verification IP (VIP) components.
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- Collaborate with third-party VIP providers.
-
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Methodology and Flows:
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- Demonstrate a solid understanding of ASIC design and verification
- methodologies.
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- Apply object-oriented programming principles effectively.
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- Implement constraint random verification methodology.
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Technical Skills:
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- Proficiency in SystemVerilog (OVM/UVM) and other relevant languages
- (C/C++, Perl, Tcl, Python, Verilog PLI).
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- Familiarity with industry standards (e.g., I2C/SPI).
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- Experience with low-power verification using UPF (Unified Power Format) is
- a plus.
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- Knowledge of formal verification techniques is advantageous.
-
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Collaboration and Communication:
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- Work effectively with internal teams and external customers.
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- Strong written and verbal communication skills.
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- Initiative, analytical problem-solving abilities, and adaptability within
- a diverse team environment.
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#LI-RG1
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here
https: //www.onsemi.com/careers/career-benefits
[https: //www.onsemi.com/careers/career-benefits]
We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.