Role & seniority: Senior Verification Engineer (IP/SoC level) focused on Infinity Fabric network on chip verification.

Stack/tools: SystemVerilog / UVM, testbench development; BFM/UVC development; scripting (Perl, Ruby, Make); OO-based code; exposure to C++; RTL/design/formal verification familiarity.

Top 3 responsibilities

Develop and enhance SystemVerilog/UVM-based testbenches to verify new features of client/server/graphics/semi-custom interconnects.
Develop and refine BFM/UVCs for industry-wide and AMD internal protocols.
Collaborate with architects, hardware engineers, and multiple IP teams; mentor junior engineers; engage across RTL/design and post-silicon validation activities.

Must-have skills

7–12 years in verification, with proven SystemVerilog/UVM testbench experience at IP/SoC level.
Strong testplan creation/execution in metric-driven environments.
Experience building/refactoring testbenches, UVCs, or BFMs using OO principles; scripting skills (Perl/Ruby/Make); exposure to RTL/design or formal verification.

Nice-to-haves

C++ experience; broader exposure to software development, formal verification, or related domains.
Prior work on complex interconnects or Infinity Fabric-like architectures; post-silicon validation exposure.
Location & work type: Santa Clara, CA; Hybrid work model (#LI-Hybrid).

Full Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The Infinity Fabric network on the chip verification team is growing and looking for qualified candidates to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed for AI/ML, Client, Server, Graphic Accelerator, and Semi-Custom markets.

The Person

The preferred candidate will have proven experience verifying complex design blocks at the IP or SoC level using SystemVerilog/UVM or related technologies. He or she should be comfortable creating and executing on testplans in collaboration with design and verification colleagues in a metric-focused environment.

Key Responsibilities

Develop and enhance SystemVerilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects.
Develop and enhance BFM/UVC for industry-wide and AMD internal protocols.
Collaborate with architects, hardware engineers and multiple IP development groups.
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
Mentor junior engineers.

Preferred Experience

Architected and developed complex verification environments in SystemVerilog or C++ and infrastructure, including scripting using Perl, Ruby, Make, or the likes.
Experience in developing or refactoring testbench, UVC, or BFM code using Object-Oriented Programming (OOP) principles.
Exposure to RTL design, software development, formal verification, or other related domains.
7-12 years industry experience is preferred.

Academic Credentials

BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science.

Location

Santa Clara, CA
#LI-MR1
#LI-Hybrid

Infinity Fabric Verification Engineer