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Xsight Labs • Kiryat Gat, South District, Israel
Role & seniority: Senior Hands-on ETH SerDes Validation Engineer (5+ years in high-speed SerDes/signal integrity)
Keysight platforms: BERTs, oscilloscopes, AWGs, jitter sources, channel emulators (ISI), PNA/M8040A variants, N5991/8040/8160 familiarity preferred
Automation: Python, Shell scripts (Ubuntu), SQL for data analysis
Technologies: 112G/224G PAM4, IEEE Ethernet (802.3ck/802.3db and beyond), channel loss and equalization, jitter decomposition
End-to-end validation of 112G/224G SerDes PHYs at silicon, package, and system levels
Execute compliance, characterization, and stress tests; debug SI issues across silicon, package, PCB, connectors, and cables
Build/maintain automation for test setup, data collection, analysis, and reporting; document methodologies and results
5+ years in high-speed SerDes validation or signal integrity
Hands-on 112G PAM4 SerDes validation
Proficient with Keysight validation platforms and automation APIs
Programming: Python, Shell, SQL for data analysis
Deep understanding of PAM4, jitter decomposition, BER/margining, channel loss/equalization
Solid grasp of Ethernet/IEEE/OIF standards
Independent lab work and issue closure
Experience with 224G SerDes validation or early silicon bring-up
Familiarity with Keysight N5991/8040/8160, PNA, M8040A
Validation of 112G/224G Ethernet and interoperability/comp
About the Role We are looking for a hands-on ETH SerDes Validation Engineer to lead and execute 112G and next-generation 224G SerDes validation activities. The role involves deep lab work with Keysight test equipment, automation development, and direct execution of compliance and characterization tests according to industry standards. This position is ideal for an engineer who combines strong signal-integrity fundamentals, standards expertise, and automation-driven validation in high-speed silicon and system environments.
Key Responsibilities Perform end-to-end validation of 112G / 224G SerDes PHYs at silicon, package, and system levels Execute compliance, characterization, and stress tests for high-speed serial links
Required Qualifications
B. Sc. or M.Sc. in Electrical Engineering or equivalent
Preferred Qualifications Experience with 224G SerDes validation or early silicon bring-up Familiarity with Keysight N5991 / 8040 / 8160 / PNA / M8040A platforms
What We Offer Work on cutting-edge 112G / 224G SerDes technologies Direct impact on next-generation silicon and systems Advanced lab environment with state-of-the-art Keysight equipment Highly technical, expert-level team Competitive compensation and benefits Location in Kiryat Gat with access to major semiconductor programs