Role & seniority: FPGA Verification Engineer, mid-senior to senior (≥5 years in block-level verification)

Stack/tools: FPGA/ASIC verification; UVM, SystemVerilog, Verilog; Python; communication protocols I2C, SPI, MDIO; PCIE; test planning, constrained-random environments, coverage analysis

Top 3 responsibilities

Own the verification process for the entire FPGA design
Collaborate with design engineers to derive specs and verification scenarios
Create test plans, constrained-random environments, test cases, regressions, and coverage reports; develop and manage coverage for stimuli and corner cases

Must-have skills

≥5 years design verification experience at block level; simulations for FPGA/ASIC
Proficiency in FPGA verification, UVM, SystemVerilog, Verilog
Experience with I2C, SPI, MDIO; ability to create/debug test cases involving control paths and PCIe
Python programming

Nice-to-haves

Experience building an environment/framework from scratch
Experience applying AI to improve verification workflows

Location & work type: Contract position in San Jose, CA; onsite 4 days/week (Mon–Thu), optional remote Fridays; initial 12-month term with strong likelihood of extension beyond 24 months

Full Description

Job Title: FPGA Verification Engineer

Job Description

As an FPGA Verification Engineer, you will take ownership of the verification for the entire FPGA verification used in high-end router products. You will work closely with design engineers to understand design specifications and identify verification scenarios.

Responsibilities

Own the verification process for the entire FPGA design. Collaborate with design engineers to understand specifications and identify verification scenarios. Create test plans, constrained-random verification environments, test cases, regressions, and coverage reports. Identify and write all types of coverage measures for stimulus and corner cases.

Essential Skills

Minimum of 5 years of design verification experience at the block level and running simulations for either FPGAs or ASICs. Proficiency in FPGA, design verification, UVM, SystemVerilog, and Verilog. Experience with communication protocols like I2C, SPI, and MDIO. Ability to create and debug test cases involving control paths and PCIE. Knowledge of Python.

Additional Skills & Qualifications

Experience building an environment and framework from scratch is a huge plus. Experience using AI to enhance work processes.

Work Environment

This role requires onsite presence 4 days a week (Monday to Thursday), with the flexibility to work from home on Fridays unless specific tasks require onsite attendance. You will be part of a team supporting the high-end routing business group, working on next-generation routers. This position offers the opportunity to own FPGA verification projects. While the initial duration is 12 months, there is a realistic expectation for the contract to extend beyond 24 months as most consultants in this role tend to exceed this timeframe.

Job Type & Location

This is a Contract position based out of San Jose, CA.

Pay And Benefits

The pay range for this position is $50.00 - $60.00/hr.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following

Medical, dental & vision Critical Illness, Accident, and Hospital 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available Life Insurance (Voluntary Life & AD&D for the employee and dependents) Short and long-term disability Health Spending Account (HSA) Transportation benefits Employee Assistance Program Time Off/Leave (PTO, Vacation or Sick Leave) Workplace Type This is a fully onsite position in San Jose,CA. Application Deadline This position is anticipated to close on Mar 5, 2026.