Full Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. We are looking for a Physical Verification Engineer to join our VLSI design team. In this role, you will own the physical verification signoff for complex SoCs and IP blocks at advanced process nodes (5nm and below). You will work closely with physical design, DFT, and PDK teams to ensure design correctness, yield, and tape-out readiness. Key responsibilities Lead DRC, LVS, ERC, and antenna checks for full-chip and block-level designs at advanced nodes (5nm / 3nm / 2nm). Drive physical verification closure and own signoff for tape-out milestones. Develop and maintain runsets, waiver flows, and automation scripts for efficient verification turnaround. Collaborate with PDK and foundry teams (TSMC, Samsung, Intel Foundry) to resolve rule interpretation issues. Perform DFM (Design for Manufacturability) analysis including CMP, density, and litho checks. Integrate physical verification into the design flow using Calibre, PVS, or IC Validator toolsets. Debug and root-cause complex DRC/LVS violations in collaboration with physical design engineers. Mentor junior engineers and establish best practices for the verification flow. Generate and review physical verification reports for design reviews and customer sign-offs. Required qualifications Bachelor's or Master's degree in Electronics Engineering, VLSI, or a related field. 7+ years of hands-on physical verification experience in semiconductor / VLSI design. Deep expertise in DRC, LVS, ERC, and antenna rule checks in production tape-out environments. Experience at advanced process nodes (7nm and below); 5nm / 3nm is a strong plus. Proficiency with Mentor Calibre (primary) and/or Synopsys IC Validator / Cadence PVS. Strong scripting skills in Python, Tcl, or SKILL for flow automation. Solid understanding of CMOS layout, design rules, and full-chip physical design flows. Experience with major foundry PDKs (TSMC, Samsung, or equivalent). Preferred qualifications Exposure to FinFET / GAA device physics and associated layout constraints.

Experience with DFM checks: CMP, pattern density, litho-friendly design. Familiarity with parasitic extraction (StarRC / QRC) and its interaction with LVS. Prior experience leading physical verification for a full SoC tape-out. Knowledge of low-power design techniques (power domains, UPF) and their impact on verification. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.