Role & seniority: Mid-senior ASIC Design Verification Engineer

Stack/tools: SystemVerilog/UVM; testbench development; Python/Perl scripting; EDA simulators (Synopsys VCS, Cadence Xcelium, Mentor Questa); coverage-driven verification; optional formal verification tools

Top 3 responsibilities

Develop reusable verification environments (testbenches) from scratch using UVM
Define and execute verification plans, feature lists, test strategies, and coverage goals
Drive coverage closure and manage regression suites to ensure tape-out readiness

Must-have skills

3+ years in ASIC/SoC design verification
Strong UVM, SystemVerilog expertise
Proficiency in Python or Perl; experience with functional and code coverage analysis
Experience with industry-standard simulators; debugging complex digital designs
Bachelor’s or Master’s in Electrical/Computer Engineering or related field

Nice-to-haves

Verifying high-speed interfaces, SerDes, Ethernet, PCIe
Exposure to FEC, scrambling, or other data-communication techniques
Knowledge of formal verification tools (VC Formal, JasperGold)
Familiarity with low-power verification; PHY/mixed-signal concepts; HDL basics
Location & work type: Location and work type not specified in provided information; please confirm.

Full Description

About the role

Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance, and robustness of our high-speed, low-power digital integrated circuits (ICs) for groundbreaking silicon photonics and optical interconnect solutions. This position requires strong expertise in verification methodology and a commitment to quality.

Responsibilities

Testbench Development: Develop comprehensive and reusable verification environments (Testbenches) from scratch using advanced methodologies like UVM (Universal Verification Methodology).

Verification Planning: Work closely with the architecture and design teams to define and execute thorough verification plans, including feature lists, test strategies, and coverage goals.

Test Case Creation: Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and functional coverage models.

Functional Debugging: Execute simulations, analyze results, and effectively debug complex functional failures, working with design engineers to identify and resolve root causes.

Coverage Closure: Drive functional and code coverage closure, identifying coverage holes and implementing targeted tests to achieve tape-out quality.

Regression Management: Maintain and manage regression suites, optimizing simulation speed and efficiency.

Formal Verification: Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex state machines.

Scripting and Automation: Develop and maintain automation scripts (e.g., in Python or Perl) to enhance the verification flow and improve efficiency.

Qualifications

Required

Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Experience: 3+ years of professional experience in ASIC/SoC design verification.

UVM Expertise: Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM.

Verification Languages: Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl.

Tool Proficiency: Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).

ASIC Design Verification Engineer