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SEAKR Engineering • Centennial, Colorado, United States
Salary: $130,000-$165,000 per year
Role & seniority: Verification Engineer (senior); capable of leading a verification team; 10+ years of experience; US Citizenship required.
Stack / tools: SystemVerilog with UVM; simulation tools (Mentor ModelSim/QuestaSim); Verilog RTL analysis; VHDL (plus); regression testing and coverage; experience with verification IP integration.
Develop verification strategies, test plans, and coverage metrics; perform design reviews.
Architect, construct, and maintain full UVM-based test environments for complex devices; run regression suites.
Diagnose sophisticated test failures, analyze code coverage, adjust agent sequences; mentor/lead less senior engineers.
Bachelor’s in Electrical Engineering or Computer Science (Master’s preferred).
10+ years of verification engineering experience.
Proficiency with SystemVerilog/UVM, building complete test environments, and using ModelSim/QuestaSim.
Ability to analyze Verilog RTL and lead a team; work under pressure.
Experience verifying Ethernet and PCIe designs; DSP-related verification.
Verification IP integration into existing environments; VHDL knowledge (plus).
Location & work type: Remote possible, hybrid strongly preferred; US Citizenship required.
Company Description Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space. Job Description SEAKR is currently seeking a Verification Engineer who is responsible for developing verification and simulation strategies, conducting design reviews, creating a digital test plan and providing coverage metrics. The Engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test. The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements. Ability to architect and construct full test environments for complex devices using UVM, including coverage, is required. The candidate shall be capable of diagnosing sophisticated test failures and filing results, and be capable of analyzing code coverage to adjust agent sequence behavior. Ability to provide direction to less senior verification engineers is required. Ability to lead a team of verification engineers to fully verify a device is required. Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required. Ability to analyze Verilog RTL to diagnose test failures is required. Ability to analyze VHDL is a plus. Must be able to work effectively under pressure to meet tight deadlines. Experience verifying Ethernet and PCIe designs a plus. Experience using/integrating verification IP into existing environments a plus Experience verifying DSP related designs a plus. Qualifications A Bachelors degree in Electrical Engineering or Computer Science . A Master's Degree is preferred. A minimum of 10 years of verification engineering experience are required Additional Information
Compensation: Base pay range is $130,000-$165,000 per year, depending on qualifications. SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan. In addition to base salary, employees are eligible for a year-end bonus. SEAKR offers a variety of paid leave, such as vacation, sick, bereavement, and FMLA. Remote work is possible, however hybird is strongly preferred. SEAKR is an Equal Opportunity Employer - All your information will be kept confidential according to EEO guidelines. US Citizenship Required Applications will be accepted until 1/16/26
Compensation: USD130000 - USD165000 - yearly