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SEAKR Engineering • Centennial, Colorado, United States
Salary: $130,000 - $165,000 / year
Role & seniority: Verification Engineer, senior/lead level (requires ability to lead a verification team)
Stack / tools: SystemVerilog with UVM; regression testing; simulation tools (Mentor Graphics ModelSim/QuestaSim); RTL analysis (Verilog; VHDL a plus); experience integrating verification IP
Develop verification and simulation strategies; construct and maintain full test environments with coverage
Lead and mentor a team of verification engineers; diagnose complex test failures and adjust coverage/agent behavior
Conduct design reviews; create digital test plans and provide results/metrics
10+ years in verification engineering
Expertise in SystemVerilog/UVM and building full testbenches with coverage
Proficient in RTL analysis (Verilog; VHDL a plus) and regression testing
Experience with Mentor ModelSim/QuestaSim; ability to work under tight deadlines
Strong communication and leadership capabilities
Experience verifying Ethernet, PCIe designs
DSP design verification experience
Verification IP integration into existing environments
Location & work type: US-based; Hybrid work strongly preferred (Remote possible); US citizenship required
Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space.
Job Description
SEAKR is currently seeking a Verification Engineer who is responsible for developing verification and simulation strategies, conducting design reviews, creating a digital test plan and providing coverage metrics.
The Engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test. The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements. Ability to architect and construct full test environments for complex devices using UVM, including coverage, is required. The candidate shall be capable of diagnosing sophisticated test failures and filing results, and be capable of analyzing code coverage to adjust agent sequence behavior. Ability to provide direction to less senior verification engineers is required. Ability to lead a team of verification engineers to fully verify a device is required. Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required. Ability to analyze Verilog RTL to diagnose test failures is required. Ability to analyze VHDL is a plus. Must be able to work effectively under pressure to meet tight deadlines. Experience verifying Ethernet and PCIe designs a plus. Experience using/integrating verification IP into existing environments a plus Experience verifying DSP related designs a plus.
Qualifications
A Bachelors degree in Electrical Engineering or Computer Science . A Master's Degree is preferred. A minimum of 10 years of verification engineering experience are required
Additional Information
Compensation: Base pay range is $130,000-$165,000 per year, depending on qualifications. SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan. In addition to base salary, employees are eligible for a year-end bonus. SEAKR offers a variety of paid leave, such as vacation, sick, bereavement, and FMLA.
Remote Work Is Possible, However Hybird Is Strongly Preferred.
SEAKR is an Equal Opportunity Employer - All your information will be kept confidential according to EEO guidelines.
US Citizenship Required
Applications will be accepted until 3/13/26