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Micron Technology • Tlaquepaque, Jalisco, Mexico
Role & seniority: Senior IC verification architect / design-flow engineer (5–8 years in IC design flow development, memory/mixed-signal focus)
Stack/tools: Calibre SVRF/TVF; SKILL; Perl; Python; Bash; C-shell; HSPICE; Finesim; schematic entry; netlist extraction; post-layout verification; LVS/DRC/PEX; Calibre rule deck coding; Confluence/SharePoint; ML knowledge optional
Architect, develop and coordinate verification flows, methodologies and automation for scribe design-specific simulation and physical verification
Collaborate with Process Integration, CAD and PDK teams to resolve physical verification rule deck issues
Implement automation scripts and maintain/analyze design flows (Calibre SVRF/TVF, SKILL, Python, etc.) across front-end and back-end analog/mixed-signal processes
5–8 years in IC design flow development for memory/mixed-signal design and layout
Strong understanding of front-end/back-end analog/mixed-signal design flows and methodologies
Proficient with SPICE simulators (HSPICE, Finesim); schematic entry; netlist extraction; post-layout verification
Experience with LVS/DRC/PEX and Calibre SVRF/TVF rule decks; automation scripting (SKILL, Perl, Python, Bash, C-shell)
Ability to work in cross-functional, multi-site teams across time zones
Knowledge of physical verification rule deck coding beyond basics
Background in machine learning algorithms/methodologies
Responsibilities will include, but are not limited to: Architect, develop and coordinate verification flows/methodologies/automation solutions for scribe design specific simulation and physical verification methodologies. Collaborate with Process Integration, CAD and PDK teams to resolve physical verification rule deck issues. Implement automation scripts in Calibre SVRF/TVF, SKILL, Perl, Python, Bash and C-shell. Master's or higher degree in Electrical/Electronics Engineering or related field. 5-8 years of relevant experience in the fields of IC design flow development, Memory/Mixed-Signal Design and Layout. Understanding front-end, back-end analog and mixed signal design flows and methodologies is a must. Knowledge of spice simulators such as HSPICE and Finesim. Hands on experience with schematic entry, netlist extraction, and post layout verification. Familiarity with semiconductor electrical fundamentals and device physics. Capable of working in a cross-functional and multi-site team environment spanning multiple time zones. Experience in automation of IC design flows using SKILL, Perl, Python, Bash, C-Shell coding. Understanding of physical verification flows like LVS, DRC, PEX rule deck coding using Calibre SVRF/TVF is a plus. Knowledge in the area of machine learning algorithms and methodologies. Experience in maintaining intranet portals such as confluence and sharepoint. "The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position." We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.