
Staff Machine Learning ASIC Design Verification Engineer
Qualcomm • Markham, Ontario, Canada
Role & seniority: ASIC Design Verification Engineer (senior/experienced level; 4+ years required, or 3+ with Master, 2+ with PhD)
Stack/tools: Verilog/SystemVerilog (UVM), SystemC; HDL: Verilog/SystemVerilog; HVL: SystemVerilog testbenches; languages: C/C++, Python, Perl, TCL; build/scripts: GNU Make; familiarity with VCS/Verdi/Modeltech-Questa/Xcelium; knowledge of display/bus protocols (AHB/AXI, MIPI, HDMI/DisplayPort) recommended
Top 3 responsibilities
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Verifies, validates, integrates ASIC hardware for AI/ML HW IP; develops verification environments and test plans
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Debugs complex issues across digital RTL and verification components; analyzes risk and mitigates defects
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Collaborates with design, architecture, and software teams to ensure correct functionality and timing
Must-have skills
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Strong analytical and debugging abilities; solid C/C++ proficiency; OOP concepts
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Deep experience with SystemVerilog/UVM or SystemC; Verilog/SystemVerilog RTL delivery
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Digital circuits knowledge, event-driven simulators, scripting (Python, Perl, TCL), and task planning
Nice-to-haves
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Experience delivering Verilog/SystemVerilog RTL; clock domain crossing, reset architectures; ML/HW development
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Experience with memory, FIFOs, bus verification (AHB/AXI), high-speed/low-power design optimization
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Tools: coverage, CDC/SVA assertions, Spyglass/0-in, UPF/Power analysis, Primetime, Formal tools
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On-site Canada work eligibility; collaboration and communic
Full Description
Company
Qualcomm Canada ULC
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
QUALCOMM is the world's leading developer of next-generation wireless and multimedia technology.
We are searching for an ASIC design verification engineer interested in developing world-class solutions for the next generation of AI/ML HW IP.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Required Skills/Experience
Strong analytical and debugging skills Good working experience with C/C++ Strong knowledge of Object Oriented Programming (OOP) concepts
Hardware verification languages (HVL): SystemVerilog testbench (UVM), and/or SystemC
Hardware description languages (HDL): Verilog and SystemVerilog
Knowledgeable in one or more of the following disciplines is preferred: Display (Pixel processing/composition/compression, MIPI DSI, DisplayPort, HDMI etc.), Bus/interconnect (AHB, AXI) Strong knowledge of digital circuits and event-driven simulators Knowledgeable with Perl, Python, TCL, tcsh, and GNU Make Strong communication skills (written and verbal) to convey complex information to peers. Detailed oriented and be able to plan and prioritize tasks effectively.
Preferred Qualifications
Prior experience delivering Verilog and/or System Verilog RTL Detail oriented with strong analytical and debugging skills Strong communication (written and verbal), collaboration, and specification skills
Practiced working experience with some of the following concepts
- Clock domain crossing and reset architecture
- Machine Learning HW development
- FIFOs implementation
- Bus implementation/verification techniques
- Memory selection and control
- High speed and low power design optimization
- Bus interface protocols (AHB, AXI)
- Experience with some of the following
- Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)
- Design rule and CDC checking (SVA assertions, Spyglass, 0-in, etc.)
- Scripting languages (PERL, Python, TCL, C, etc.)
Power Intent and Analysis: UPF, CLP, PTPX, PowerPro
Synthesis: DCG/NXT, FC
Static Timing: Primetime
Formal Verification: Conformal, Formality Legally permitted to work on-site in Canada 5+ years of ASIC design, verification, or related work experience.
Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
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Pay Range And Other Compensation & Benefits
$124,200.00 - $174,200.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.
If you would like more information about this role, please contact Qualcomm Careers.