Role & seniority

ASIC design verification engineer (mid senior level; 4+ years experience with bachelor’s, 3+ with master’s, or 2+ with PhD)

Stack/tools

HDL/verification: Verilog, SystemVerilog, SystemVerilog UVM, SystemC

Languages: C/C++, Perl, Python, TCL; GNU Make

Debug/diagnostics: VCS, Verdi, Modeltech/Questa, Xcelium; SVA, 0-in, Spyglass

Design concepts: clock domain crossing, reset architecture, memory/select/bus (AHB, AXI)

Optional: UPF/CLP/PTPX power, synthesis (DCG/NXT, FC), formal (Conformal/Formality), static timing (Primetime)

Top 3 responsibilities

Develop, implement, and maintain ASIC verification environments and testbenches for AI/ML HW IP
Debug complex verification failures, analyze/triage issues, and ensure functional and timing coverage
Collaborate with design/architecture teams to validate RTL, implement coverage-driven verification, and deliver verified IP

Must-have skills

Bachelor’s in Science/Engineering (or higher) with 4+ years (MS 3+, PhD 2+)
Strong debugging and analytical skills; excellent written/verbal communication
Proficiency in C/C++, SystemVerilog/UVM, and Verilog/SystemVerilog; digital circuit knowledge
Experience with HVL/HVL toolchains, event-driven simulators, and one or more interconnect/bus domains
Ability to plan, prioritize, and work on-site in Canada

Nice-to-haves

Prior RTL delivery of Verilog/SystemVerilog
Experience with ML HW development, FIFOs, memory control, high-speed/low-power design
Exp

Full Description

Company

Qualcomm Canada ULC

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

QUALCOMM is the world's leading developer of next-generation wireless and multimedia technology.
We are searching for an ASIC design verification engineer interested in developing world-class solutions for the next generation of AI/ML HW IP.

Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Required Skills/Experience

Strong analytical and debugging skills
Good working experience with C/C++
Strong knowledge of Object Oriented Programming (OOP) concepts

Hardware verification languages (HVL): SystemVerilog testbench (UVM), and/or SystemC

Hardware description languages (HDL): Verilog and SystemVerilog

Knowledgeable in one or more of the following disciplines is preferred: Display (Pixel processing/composition/compression, MIPI DSI, DisplayPort, HDMI etc.), Bus/interconnect (AHB, AXI) Strong knowledge of digital circuits and event-driven simulators Knowledgeable with Perl, Python, TCL, tcsh, and GNU Make Strong communication skills (written and verbal) to convey complex information to peers. Detailed oriented and be able to plan and prioritize tasks effectively.

Preferred Qualifications

Prior experience delivering Verilog and/or System Verilog RTL
Detail oriented with strong analytical and debugging skills
Strong communication (written and verbal), collaboration, and specification skills

Practiced working experience with some of the following concepts

Clock domain crossing and reset architecture
Machine Learning HW development
FIFOs implementation
Bus implementation/verification techniques
Memory selection and control
High speed and low power design optimization
Bus interface protocols (AHB, AXI)
Experience with some of the following
Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)
Design rule and CDC checking (SVA assertions, Spyglass, 0-in, etc.)
Scripting languages (PERL, Python, TCL, C, etc.)

Power Intent and Analysis: UPF, CLP, PTPX, PowerPro

Synthesis: DCG/NXT, FC

Static Timing: Primetime

Formal Verification: Conformal, Formality Legally permitted to work on-site in Canada 2+ years of ASIC design, verification, or related work experience.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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Pay range and Other Compensation & Benefits

$124,200.00 - $174,200.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.
If you would like more information about this role, please contact Qualcomm Careers.

Machine Learning ASIC Design Verification Engineer