CAD Engineer – Design Verification Methodology
Apple • Waltham, Texas, United States
Role & seniority: Mid-level hardware/software engineer (BS + ~3+ years) within Apple’s Silicon Technologies/CAD team. Focus on regression-testing silicon designs and tool integration.
Stack/tools: Python; TCL/Perl (plus); Verilog/SystemVerilog (VHDL a plus); EDA tools (Synopsys VCS, Xcelium, ModelSim); debugging vendor tools; Verdi/Indago; Makefiles; C/C++.
Top 3 responsibilities
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Develop, maintain, and enhance regression-testing software for RTL-based silicon designs and software simulations to find defects before tape-out.
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Debug vendor tool problems; work with DV teams to solve issues and optimize regression flows.
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Integrate new tool capabilities from EDA vendors; implement new functionality to address emerging problems and improve existing methods.
Must-have skills
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BS degree with 3+ years’ relevant Python programming experience.
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Experience debugging vendor tools and regressing RTL.
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Familiarity with Verilog/SystemVerilog; scripting or Makefile work to build simulation models is a plus.
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Strong problem-solving, debugging, and communication abilities.
Nice-to-haves
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TCL or Perl experience; AI/ML exposure; DV-team collaboration experience.
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MSEE/CE/CS preferred; VHDL familiarity.
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Experience with Synopsys VCS/XCelium/ModelSim; Verdi/Indago familiarity; C/C++ skills.
Location & work type: Not specified in the description; details on location and work arrangement are not provided.
Full Description
Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!
DESCRIPTION
As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple’s silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple’s DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems.
MINIMUM QUALIFICATIONS
Minimum of BS degree + 3 years of relevant experience Python programming background
PREFERRED QUALIFICATIONS
Experience debugging vendor tool problems Experience developing, maintaining, and enhancing an existing system for regressing RTL Experience with TCL or Perl is a plus Experience with artificial intelligence and machine learning Experience with interacting with DV team(s) to help solve their problems. Experience in implementing new functionality to solve emerging problems or to optimize already existing methods. MSEE/CE/CS preferred Knowledge in Verilog and SystemVerilog; familiarity with VHDL a plus Experience with Synopsys VCS, XCelium, or Modelsim Good communications skills are required and prior customer support experience is a plus Experience writing or maintaining a script or Makefile that builds a simulation model from RTL is a plus Familiarity with Verdi and/or Indago is considered a plus Knowledge of C and C++ is a plus
