Full Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

• AMD is looking for an experienced Design Verification Engineer willing to take on the challenge of verifying a leading edge PCIe Controller Design. In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD SOCs powering AI Training and Inference, Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team is responsible for the Verification of several critical blocks, interoperability of lower level IPs and the SubSystem delivery to SoC. The team is tasked with verifying a balanced architecture between power consumption and performance, delivering high complexity RTL code and Verification components, as well as creating advanced testbenches using leading-edge verification techniques.

THE PERSON

• A successful candidate will work with architects and fellow design and verification engineers. The candidate will be highly accurate and detail-oriented, possessing strong communication, technical, leadership and problem-solving skills. Can work well with cross functional teams. Skilled at driving tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones.

KEY RESPONSIBLITIES

• Work on functional verification execution from test plan to verification signoff.
• Collaborate with architects and designers to understand the IP features.
• Write/Implement/Review Test Plans.
• Verification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification.
• Own some or all aspects of the Verification flow from initial test planning to coverage convergence and sign-off closure for one or more features and aspects of SubSystem level IP interoperability.
• Build testbench components and develop test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology.