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Qualinx • Delft, South Holland, Netherlands
Role & seniority
Stack/tools
Digital ASIC verification, SystemVerilog, UVM
RTL, post-layout simulation for mixed-signal SoCs
EDA tools: Cadence, Mentor; RTL/logic synthesis, timing analysis (STA)
Programming/scripting: MATLAB, C/C++, Tcl
DFT/ECO flows, CDC, lint, PNR, back-annotation of parasitics
Top 3 responsibilities
Lead verification of digital IP blocks and chip-level post-layout simulations; define verification/test plans; develop benches and test cases for block-level verification
Collaborate with backend/implementation to resolve synthesis, timing, DFT issues; oversee Lint, CDC, Synthesis, ECO; drive timing closure and sign-off readiness
Verify IP integration at top-level SoC, manage clock-domain interfaces, scan testing, memory BIST, and test-pattern generation; guide design-for-test methodology
Must-have skills
10+ years ASIC verification experience; couple years in a team lead role
Proficiency with Verilog; strong experience with SystemVerilog/UVM
Deep knowledge of digital design flow: RTL sim, synthesis, timing constraints, STA; netlist verifications
Experience with mixed-signal/analog blocks and ultra-low-power designs; digital backend flows (Floorplanning/Place & Route)
CDC techniques, DFT/ECO flows, power intent and distribution, clock-domain crossing
Strong analytical/problem-solving ability; solid programming/scripting (MATLAB, C/C++, Tcl)
Nice-to-haves
Who are we? Imagine being part of the dynamic journey at Qualinx – a startup born when three visionary PhD Engineers from TU Delft set out to revolutionize radio chip technology. At Qualinx, we're on a mission to conquer the high-power consumption challenges in Global Navigation Satellite Systems and IoT sensors. With a great team of over 40 individuals, scaling to 60 next year, hosting more than 18 nationalities, we've achieved the impossible - the world's lowest power GNSS chipset. Now, we're on the verge of unleashing our game-changing digital RF technology product, ready to flood the market with millions of annual shipments.
What Sets Us Apart Joining Qualinx isn't just about a job; it's about embracing high standards, and boldly navigating unexpected challenges. We thrive on collaboration, with a commitment to self-improvement and product excellence. At Qualinx, you're not just an employee; you're an integral part of our exciting journey, contributing to the growth and success of a ground breaking solution.
Job Description As a Team Lead Digital ASIC Verification Engineer, you'll play a role in shaping the future of our cutting-edge technology. You will be responsible for the verification of our digital IP blocks and the simulation of Chip level post-layout within our upcoming SoCs. You will contribute to the circuit design for our next-generation products. You are responsible for ASIC verification, System Verilog, and UVM. You will be responsible for the simulation and verification of digital block implementation in RTL for various functions, including control state machine digital processing (DSP), and multiple clock domain interface management. During your work at Qualinx you will be responsible for the post-layout simulation of complex mixed-signal SoC. As a Digital ASIC Verification engineer you will develop test benches and test cases for block-level functional verification. You will work with our backend and implementation teams to address synthesis, timing, DFT issues for the ASIC implementation. You understand all design integration activities like Lint, CDC, Synthesis & ECO. You will define the verification and test plan, run regressions, reproduce, and debug functional and performance bugs. You are responsible for the verification of various IPs/Sub IPs integrated to the top level SoC.
Lastly: you will have an understanding of the design synthesis and fix timing issues for the Physical Design team.
Requirements
You have strong programming and scripting skills: MATLAB, C/C++, Tcl Experience in setting up Power Distribution architecture, power intent specification and validation methodology. Strong knowledge of clock domain crossing (CDC) techniques. Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation Strong analytical, problem-solving skills.
What's in it for you? Given that we are a startup, we provide all our employees with Stock Appreciation Rights. You will be eligible to financially profit from Qualinx's success. We support you in your visa process if needed.
Saving for your pension: we provide an extra 2% of your monthly base salary. 25 vacation days based on a 40-hour workweek. Work in a beautiful and modern office with all the necessary equipment you need to deliver a great job. Every quarter we organize fantastic social events, where we celebrate the success of Qualinx by going out for a great meal, playing VR games, going bowling, etc. At Qualinx we invest in the development of our employees, we offer Quarterly Lunch & Learn sessions to keep everyone who is interested up to speed.