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Apple • California, United States
Role & seniority: SerDes Robustness Analysis & Validation Architect (senior-level); hands-on, leading validation strategy and execution
Stack/tools: SerDes PHY validation (PCIe, USB, Ethernet, DisplayPort); lab instrumentation (oscilloscopes, BERTs, protocol analyzers); SI/PI concepts; equalization (CTLE, DFE, FFE); multi-lane PHYs; programming/data analysis (Python, C/C++)
Architect and drive validation strategies beyond spec-checking to uncover design weaknesses, stress-to-fail scenarios, and system interactions across wide PVT/real-world conditions
Collaborate with design, architecture, system and validation teams to maximize test coverage while minimizing execution time; ensure design-for-testability
Lead hands-on lab validation from concept through production, perform fault injection and post-silicon insights to inform future design changes
BS + 10+ years or PhD + 10+ years in SerDes IP validation, AMS/analog/mixed-signal design, or silicon/system debug
Deep knowledge of high-speed serial protocols (PCIe, USB, Ethernet, DisplayPort) and equalization (CTLE/DFE/FFE)
Strong SI/PI understanding; lab experience with oscilloscopes, BERTs, protocol analyzers; programming (Python, C/C++); data analysis and validation automation
Ability to break down complex problems, root-cause across circuit/protocol/system levels; experience with design-for-validation, fault injection, and multi-lane PHYs
Nice-to-h
Are you inherently curious, hands-on, and analytical? We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of high-speed SerDes PHYs, such PCIe and USB, within our system. This role is ideal for someone who is motivated to push designs to the edge through intentional stress testing and margin-finding techniques!
DESCRIPTION
You will architect validation strategies that go beyond traditional spec-checking, focusing on uncovering weaknesses in design assumptions, stress-to-fail conditions, and system interactions across wide-ranging PVT and real-world scenarios, including edge case behaviors. A deep understanding of SerDes design and validation principles, SOC/system integration, and real-world system environments is required. The role demands strong collaboration with design, architecture, and system teams to ensure the IP is designed with design for testability. In addition, you will also partner closely with the validation team to help optimize for maximum test coverage vs. execution time, ensuring efficient yet thorough validation. This is a hands-on lab role that requires close collaboration with designers, architects, system, and test engineers to validate next-generation SerDes IPs from design conception through production.
MINIMUM QUALIFICATIONS
BS and 10 +years of relevant industry experience
PREFERRED QUALIFICATIONS
PhD in Electrical Engineering or related field with 10+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug. Hands-on lab experience with lab instrumentations such as oscilloscopes, BERTs, protocol analyzers, etc, and measurement setups tailored for SerDes PHYs. Deep understanding of high-speed serial link protocols (PCIe, USB, Ethernet, DisplayPort, etc.) and equalization techniques (such as CTLE, DFE, FFE, etc.) Strong foundation in analog/mixed-signal design principles and familiarity with signal integrity (SI) and power integrity (PI) impacts. Skilled in programming (Python, C/C++, etc.) and data analysis tools for validation automation and correlation studies. Proven ability to break down complex problems, isolate issues, and root-cause at the circuit, protocol, and system levels. Demonstrated experience in design-for-validation, including fault injection, internal monitors, and behavioral hooks. Experience validating multi-lane PHYs with adaptive EQ, clocking and CDR paths, and challenging compliance requirements in various real systems. Familiarity with production and characterization flows, including margin-to-fail and stress testing techniques. Ability to guide test coverage optimization to reduce execution time without sacrificing risk coverage. Experience providing post-silicon insights that shaped future design changes. Passion for deep debug and a “find the flaw” mentality, with an interest to explore the unexpected.