HBM Design Verification Engineer, Principal
Synopsys Inc • Hsinchu, Taiwan
Role & seniority: Senior/Principal Verification Engineer (ASIC/SoC verification lead)
Stack/tools: SystemVerilog, UVM (and variants VMM/OVM), Verilog/SystemVerilog, testbench architecture, constraint random verification, coverage models, checkers; Unix-based environments; optional: C/C++, Python, Perl, TCL scripting; familiarity with DDR, PCIe, AMBA (AXI/CHI), SD/eMMC, Ethernet, USB, MIPI; verification tooling and simulation environments
Top 3 responsibilities
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Develop verification strategies/plans, define/testbench architecture, and build verification infrastructure
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Create verification items, coverage models, checkers; provide metric-driven verification progress reports
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Lead design reviews, mentor teammates, break down tasks, manage schedules/deliverables; act as technical expert
Must-have skills
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BSEE/MSEE with 10–15+ years in ASIC/SoC verification
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Deep hands-on experience creating test environments from specs using UVM/VMM/OVM
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Expertise in constraint random verification, coverage closure, failure analysis; SystemVerilog/uVM; Verilog/SystemVerilog; SoC/ASIC design flows; Unix proficiency; strong written/verbal English; independent problem solving; strong teamwork
Nice-to-haves
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Formal verification experience; C/C++, Python, Perl, TCL scripting
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Firmware/embedded software understanding; functional safety knowledge (ISO26262, FMEDA)
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Experience with other interfaces (DDR, PCIe, AMBA, SD/eMMC, Ethernet, USB, MIPI)
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Location & work t
Full Description
About Synopsys
At Synopsys, we drive the innovations that shape how we live and work—self-driving cars, artificial intelligence, cloud computing, 5G, and the Internet of Things. As a leader in advanced chip design and software security technologies, we empower the Era of Smart Everything. If you share our passion for innovation, we invite you to join our team.
About Silicon IP
Our Silicon IP business enables customers to integrate advanced capabilities into SoCs quickly and efficiently. We offer the industry’s broadest portfolio of silicon IP, including logic, memory, interfaces, analog, security, and embedded processors. Our solutions help customers meet unique application requirements and accelerate differentiated product delivery with reduced risk.
Job Responsibilities
Develop verification strategies and plans for ASIC/SoC projects Define and implement testbench architecture and methodologies Build testbench infrastructure and verification components Create verification item lists, coverage models, and checkers Provide clear, metric-driven reports on verification progress Break down tasks, develop schedules, and manage deliverables Lead and coordinate design review meetings Serve as a technical expert and mentor within the team
Key Qualifications
Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with 10–15+ years of relevant experience Extensive hands-on experience creating test environments from functional specifications using UVM/VMM/OVM Proven expertise in constraint random verification, coverage closure, and failure analysis Proficiency in SystemVerilog, UVM, and object-oriented verification methodologies Experience with Verilog/SystemVerilog coding and simulation tools Solid understanding of SoC/ASIC design flows and backend processes
Knowledge of one or more interface protocols: DDR, PCIe, AMBA (AMBA2, AXI, CHI), SD, eMMC, Ethernet, USB, MIPI Experience working in Unix environments Strong English communication skills, both written and verbal Ability to work independently, drive innovation, and solve complex problems Strong team player with excellent interpersonal skills
Preferred Qualifications
Experience with formal verification techniques Knowledge of C/C++, Perl, Python, and TCL scripting Understanding of firmware or embedded software development Experience with functional safety standards (ISO26262, FMEDA) Show more Show less
