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Meta • Austin, Texas, United States
Salary: $178,000 - $250,000 / year
Role & seniority: Senior/Staff ASIC Formal Verification Engineer (Infrastructure group)
Stack/tools: Formal verification for IP/SoC; SystemVerilog, SVA; Datapath, sequential equivalence, Xprop, Clock Gating; EDA tools: JasperGold, VC-Formal; scripting: Python, Perl, Tcl
Lead Formal Verification efforts; define scope, environments, and coverage for IP/Subsystem/SoC blocks
Develop formal specs, verification plans, and sign-off for complex designs; build reusable scalable verification environments
Collaborate with Architecture, Design, Emulation, Full-Stack Software, and Post-Silicon teams; evangelize methodology; mentor/train engineers
8+ years in Design Verification; 5+ years in Formal Verification
Proficiency in SystemVerilog and SVA; strong formal verification methodologies
Experience with JasperGold or VC-Formal; scripting (Python, Perl, Tcl)
Experience applying formal verification to datapath, sequential equivalence, Xprop, clock gating, and connectivity
Cross-functional collaboration and analytical problem-solving
Formal verification of complex compute blocks (DSP, CPU, GPU, HW accelerators)
Clock domain crossing, IP-XACT register verification, low power
Fully automated verification flows; experience with simulators/waveform debugging
Location & work type: Location and work type not disclosed (not specified)
Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with the best in the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Responsibilities
Provide technical leadership in Formal Verification Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level Work with Architecture and Design team to come up with formal specification and implementation Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level Build reusable/scalable environments for Formal Verification and deploying the tools Evaluate and recommend EDA solutions for Formal Verification Provide training for internal teams and mentoring engineers related to Formal Verification Technology
Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of experience in Design Verification 5+ years of experience in Formal Verification Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc Proven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniques Proven analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Fluency in hardware description languages, such as SystemVerilog and SVA Proficiency in scripting languages such as Python, Perl, or Tcl Experience with JasperGold or VC-Formal
Preferred Qualifications
Experience to quickly understand and interpret specifications and extract design behaviors/properties Experience in formal property verification of complex compute blocks such as DSP, CPU, GPU or HW accelerators Experience with complex SoCs Formal verification experience in clock domain crossing, IP-XACT based register verification and low power Experience with development of fully automated flows from specification to fully verified designs Experience with simulators and waveform debugging tools
$178,000/year to $250,000/year + bonus + equity + benefits