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Apple • Cupertino, California, United States
Salary: $156,853 - $220,900 / year
Role & seniority: Design Verification Engineer (Analog & Mixed-Signal IP) – seniority not specified
Stack/tools: Verilog, SystemVerilog; C/C++; Python; UVM; scripting (Perl); DV/verification environments; pre-/post-silicon validation; mixed-signal knowledge
Create and execute pre-silicon verification plans and verification environments (stimulus, checkers, assertions, trackers, coverage)
Develop block/IP/SoC level test-benches (e.g., camera interface, USB3) and reference models; bring-up DV environment and regression
Track and report DV progress (bugs, coverage); debug test failures and ensure bug-free first silicon
Must-have skills: Master’s degree in Electrical/Computer/Electronic Engineering, CS, or related field; strong experience with Verilog/SystemVerilog; C/C++; Python; UVM; digital design/verification basics; scripting (Perl); mixed-signal concepts; post-/pre-silicon validation
Nice-to-haves: None specified
Location & work type: Cupertino, CA and various unanticipated locations across the USA; full-time, 40 hours/week; relocation may be possible; eligible for standard Apple benefits and compensation components
Note: Role focuses on ASIC IP verification for SoC components; includes plan development, DV environment creation, and rigorous regression/debug activities.
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
DESCRIPTION
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Design Verification of Analog and Mixed Signal ASIC Ips and ensure bug-free first silicon for part of the System on a Chip (SoC) / IP. Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP to ensure a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Execute verification plans, including design bring-up, DV environment bring up, regression enabling all features, and debug of the test failures .These pre silicon verification environment creation and execution helps in making sure ASIC ( Application Specific Integrated Circuits) works correctly once it is manufactured. Develop block, IP and SoC level test-benches example for camera interface, usb3 controller interface. Track and report DV progress using a variety of metrics, including bugs and coverage. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $156,853
experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.
You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or
https: //www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
MINIMUM QUALIFICATIONS
Master’s degree or foreign equivalent in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science or a related field.
Experience and/or education must include: Using Verilog, System Verilog to create complex IC verification environment to simulate pre-silicon all possible use cases. Using C and C++ to create reference model of the design under test to accurately predict the behavior. Using basics of digital design and verification to test the design and debug the failures. Using Python to enable creation of post silicon validation sequences. Using Computer Architecture to understand the use case of the soft IP cores and how it inter-operates with the various CPU sub-systems. Using UVM (Universal Verification Methodology) to create re-usable verification environments. Using scripting languages including Perl to create executable scripts. Creating validation test vectors for manufacturing tests post silicon. Using mixed-signal and signal processing knowledge/techniques to understand the Analog & Digital circuits in design and apply relevant concepts/algorithms.
PREFERRED QUALIFICATIONS
N/A