Full Description

Job Title: Design Verification Engineer

Education: B.E./B.Tech or M.E./M.Tech in Electronics / Electrical / Related disciplines

Location: : 5-12 years

Skills : SOC/ IP/Subsystem Verification

Job Summary

We are seeking a passionate and experienced Design Verification Engineer with strong hands-on expertise in System Verilog and UVM methodology.

The ideal candidate will have a solid understanding of IP- and SoC-level verification flows and experience working with complex verification environments. Exposure to GLS, UPF, and low-power verification is a plus.

Required Skills & Qualifications

Proven experience in ASIC / IP / SoC verification Strong understanding of end-to-end verification flows Experience developing and maintaining block-level, IP-level, or SoC-level testbenches

Technical Skills

Proficient in SystemVerilog and UVM Hands-on experience with testbench architecture, sequences, scoreboards, and monitors Experience working with complex verification environments using Verilog, SystemVerilog, or SystemC

Strong knowledge of AMBA protocols: AXI, AHB, APB Experience in Memory verification (DDR / DRAM) Solid understanding of functional coverage, assertions (SVA), and scoreboarding Hands-on experience with simulators such as VCS, Questa, XSIM, or equivalent Familiarity with debug and waveform analysis tools like Verdi, DVE Experience writing automation scripts using Python / Perl / TCL

Good To Have

Experience with Gate-Level Simulation (GLS) Knowledge of UPF and low-power verification Exposure to SoC-level integration and system validation

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