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Meta • Sunnyvale, California, United States
Salary: $186,000 - $192,170 / year
Role & seniority: ASIC verification engineer (mid-level to senior, with ~3+ years in verification)
Stack/tools: Verilog, SystemVerilog/UVM; block/IP/sub-system and SoC verification; EDA tools; scripting (C++, Python, Shell); test benches, functional coverage, regression setups
Develop functional tests aligned to verification test plans; build and maintain verification test benches for IP/sub-system/SoC levels
Drive design verification closure using defined metrics, coverage, and verification plans; execute full verification cycle
Debug, root-cause, and resolve functional failures; collaborate with Design, Architecture/Modeling, Emulation, and Silicon validation teams
Bachelor’s degree in Computer Science, Computer/Electrical/Electronics Engineering or related field
3+ years in Verilog/SystemVerilog/UVM-based verification; experience with block/IP/SoC verification
Proficiency with EDA tools and scripting (C++ or Python, Shell); experience building tools/flows for verification environments
Experience implementing verification infrastructure (testbenches, coverage, regression) and executing verification plans
Experience in CPU/GPU/SoC/HW accelerator verification; end-to-end verification cycles; advanced regression/coverage automation
Location & work type: Not specified in provided text.
Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.
Responsibilities
Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Define and implement ASIC verification plans, build verifications test benches to block IP/sub-system/SoC level verification and develop functional tests. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collaborate with cross-functional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality.
Minimum Qualifications
Requires a Bachelor's degree (or foreign degree equivalent) in Computer Science, Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field, followed by 3 years of work experience in the job offered or a computer-related occupation
$186,000/year to $192,170/year + bonus + equity + benefits