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Meta • Redmond, Washington, United States
Role & seniority: Verification Engineer; mid-senior level (2+ years’ hands-on experience in SystemVerilog/UVM, block/IP/SoC verification)
Stack/tools: SystemVerilog/UVM/OVM; C/C++; EDA tools; scripting (Python, TCL, Perl, Shell); verification environments for block/IP/SoC; experience with revision control (preferred)
Define and implement verification plans and build test benches for block, IP, sub-system, and SoC level verification
Develop functional tests based on the verification plan; drive verification closure using metrics, coverage, and test plans
Debug, root-cause, and resolve functional failures; collaborate with Design, Model, Emulation, and Silicon validation teams
2+ years hands-on SystemVerilog/UVM methodology
2+ years block/IP/sub-system and/or SoC level verification (SystemVerilog UVM/OVM)
Experience with EDA tools and scripting for verification workflows (Python, TCL, Perl, Shell)
Experience with revision control (Mercurial, Git, SVN)
Architecture and implementation of DV infrastructure; full verification cycle
UVM environments developed from scratch; verification of ARM/RISC-V sub-systems, CPUs/GPUs
SVA, Formal, Emulation; track record of first-pass ASIC development success
Location & work type: Location not specified; work type not specified.
Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.
Responsibilities
Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Minimum Qualifications
Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Preferred Qualifications
Experience with revision control systems like Mercurial(Hg), Git or SVN Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch Experience verifying ARM/RISC-V based sub-systems and SoCs Experience verifying CPU/GPU designs
Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycle