🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Cookies & analytics consent
We serve candidates globally, so we only activate Google Tag Manager and other analytics after you opt in. This keeps us aligned with GDPR/UK DPA, ePrivacy, LGPD, and similar rules. Essential features still run without analytics cookies.
Read how we use data in our Privacy Policy and Terms of Service.
🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Meta • Redmond, Washington, United States
Salary: $146,000 - $209,000 / year
Role & seniority: Senior/experienced verification engineer (6+ years in DV)
Stack/tools: SystemVerilog/UVM-based verification; IP/sub-system/SoC verification; C/C++; EDA tools; scripting in Python, TCL, Perl, Shell
Define/implement IP and SoC verification plans and build verification test benches for IP/sub-system/SoC level validation
Develop functional tests from the verification plan and drive Design Verification closure using metrics, coverage, and test plans
Debug and root-cause functional failures, collaborating with Design, Model/Emulation, and Silicon validation teams
6+ years in SystemVerilog/UVM/OVM-based verification for IP/sub-system and/or SoC
Hands-on experience with verification environments, test bench development, and verification flows
Proficiency with EDA tools and scripting (Python, TCL, Perl, Shell)
Experience with revision control (Git, Mercurial, SVN)
Experience architecting environment infrastructure and end-to-end DV cycle
UVM-based environments from scratch; SystemVerilog Assertions, Formal, and Emulation
Prior exposure to audio/image/video compute-intensive cores
Location & work type: Location and work type not specified; details not provided in the listing
Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.
Responsibilities
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Preferred Qualifications
Experience with revision control systems like Mercurial(Hg), Git or SVN Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch
Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation Prior working knowledge of Audio/image/Video processing compute intensive cores
$146,000/year to $209,000/year + bonus + equity + benefits