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Palo Alto Networks • Santa Clara, California, United States
Salary: $173,600 - $280,700 / year
Role & seniority: Design Verification Engineer (ASIC) – mid to senior level
Verification: SystemVerilog, UVM; coverage-driven, constrained-random testing
Platforms: simulation, emulation, formal verification, silicon validation
Automation: Python (triage, coverage closure, metrics), C/C++, UNIX shells, scripting
Test infrastructure: test benches, reference models, scoreboards
Define verification methodologies and pre-silicon verification plans across simulation, emulation, and formal verification
Plan, execute, and debug test plans; develop flows, tooling, and infrastructure; drive coverage
Create reusable test benches and self-checking infrastructure; close coverage and drive metrics; collaborate across software, architecture, design, and verification teams
BS in EE, CE, CS (MSEE preferred); 5+ years in ASIC design verification
Expertise in SystemVerilog and UVM
Strong ability to define test plans, develop coverage models, build scalable test benches, and debug failures
Proficiency in Python (automation), C/C++, and UNIX shell scripting
Experience driving verification tasks end-to-end, including regression and metrics reporting
Networking and cybersecurity experience; formal property verification
Silicon validation bring-up, testing, debugging, and regression
Experience creating models in Python/C++; driver code in C; leadership and
Our Mission
At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you’re ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you’re in the right place.
Who We Are
In order to be the cybersecurity partner of choice, we must trailblaze the path and shape the future of our industry. This is something our employees work at each day and is defined by our values: Disruption, Collaboration, Execution, Integrity, and Inclusion. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have. If you are passionate about solving real-world problems and ideating beside the best and the brightest, we invite you to join us!
We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes.
Job Summary
Your Career As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug. You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation. We expect office-based employees to be in the office four days per week, with one day working from where they choose. We believe being together facilitates casual conversations and those magic moments where we can work on issues and ideas informally. These moments build capability and deepen trusted relationships and allow our people to feel safe in taking risks and being disruptive. Like so many companies, we are working through the details and things could change …. but in general if a role is deemed office-based we want our teams to be together four days per week. Your Impact Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies Develop flows, methodologies, and infrastructure for emulation - Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers Define new tools and methodologies to continuously improve quality and velocity Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification
Qualifications
Your Experience BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred Minimum 5 years experience in ASIC design verification Demonstrated success in taking multiple ASIC products from concept to mass production Expertise in SystemVerilog and UVM Technical strength in the following areas is requiredDefining test plans, including comprehensive adversarial testing Developing rich functional coverage models Creating powerful and scalable test benches Implementing sophisticated self-checking infrastructure with reference models and scoreboards Developing reusable constrained-random tests Debugging failures Closing coverage Experience in the following areas is preferredNetworking and cyber security Formal property verification Silicon validation - bringup, test, debug, and regression Creating models in Python and C/C++ Writing driver code in C Skilled in writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status Strong leadership, collaboration, and communication skills
Compensation Disclosure
The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/com-missioned roles) is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here.
$173,600.00 - $280,700.00/yr
Our Commitment
We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.
We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations@paloaltonetworks.com.
Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.
All your information will be kept confidential according to EEO guidelines.
Is role eligible for Immigration Sponsorship? No. Please note that we will not sponsor applicants for work visas for this position.