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Worldgrid • Munich, Bavaria, Germany
Role & seniority: Verification Engineer (seniority not explicitly specified)
SystemVerilog, SystemVerilog assertions
UVM methodology
RTL and gate-level code interpretation
Scripting: Python, Perl
Formal verification methods; random-constraint testbenches
Collaboration with lab/test engineers, designers, system architects, verification engineers
Verify mixed-signal designs at block and system level using formal and functional verification
Interpret product requirements to create verification concepts and product verification specifications
Create assertions and perform random-constraint testbenches to prove designs
Engineering degree in electrical engineering, computer science, or similar
Practical experience in digital functional verification and safety standards
Programming in SystemVerilog and SystemVerilog assertions
Knowledge of UVM, Python or Perl scripting
Ability to read RTL and gate-level code
Good English communication skills
Experience with lab/test collaboration and cross-site teamwork
Familiarity with safety standards beyond baseline
Additional formal verification experience and broader tooling knowledge
Region: Bayern, Germany
Contract type: Permanent
Work style: Flexible working hours; mobile/remote possibilities; company benefits (wellbeing, bike leasing, green mobility)
Company Description We are the designers of today for the world of tomorrow. As one of the world's leading engineering service providers, we at ALTEN are committed to positively shaping the future of our partners, the careers of our employees and the challenges facing our society and environment. More than 50,000 employees in 30 countries are already working on innovative solutions in various engineering and IT sectors such as automotive, aerospace, renewable energy, medical technology and railway technology. Job Description YOU… verify mixed-signal designs on block and system level resting upon formal and functional verification interpret product requirements to create the verification concept and the product verification specification perform random-constraint testbenches according to the state of the art create assertions to prove the design using formal methods work in collaboration with lab and test engineers, designers, system architects, and verification engineers across multiple sites Qualifications YOU… have completed engineering degree in electrical engineering, computer science or similar studies already have practical experience in the field of digital functional verification and common safety standards have extensive programming skills in coding in System Verilog and System Verilog assertions have good knowledge of UVM methodology, scripting languages like Python or Perl and ability to interpret RTL and Gatelevel code have good communication skills in English We value diversity and therefore welcome all applications - regardless of gender, nationality, ethnic and social origin, religion/belief, disability, age and sexual orientation and identity. Severely disabled persons will be given preferential consideration if they are equally qualified. Do you have any questions?
Then contact me: Özlem Mumin (Tel.: +49 89 255552-331) Or apply now using our online application form. Additional Information Talent Management - we develop your career Work life balance - flexible working hours and mobile working possible Fit and relaxed – with EGYM Wellpass Enjoy biking – always on tour with bike leasing Green Mobility - with us you can travel at a reduced rate ...in addition we offer a permanent employment contract, corporate benefits and team events.
Contract Type: Permanent
Region: Bayern