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Worldgrid β’ Munich, Bavaria, Germany
Role & seniority: Digital functional verification engineer (seniority not specified)
Stack / tools: SystemVerilog, SystemVerilog assertions, UVM; RTL/Gatelevel interpretation; Python or Perl; formal verification methods; random-constraint testbenches
Verify mixed-signal designs at block and system level using formal and functional verification
Interpret product requirements to create verification concept and verification specification
Create assertions and perform testbenches to prove design correctness; collaborate with lab/test engineers, designers, system architects, and verification engineers across sites
Engineering degree in electrical engineering, computer science, or related field
Practical experience in digital functional verification and familiarity with safety standards
Strong programming in SystemVerilog and SystemVerilog assertions; good knowledge of UVM; scripting in Python or Perl
Ability to interpret RTL/Gatelevel code; good English communication
Experience with formal verification methods; knowledge of safety/regulatory standards
Cross-site collaboration experience; awareness of lab/test environments
Location & work type: Bayern, Germany; Permanent, full-time role; flexible working hours and mobile (hybrid) working options available
Company Description We are the designers of today for the world of tomorrow. As one of the world's leading engineering service providers, we at ALTEN are committed to positively shaping the future of our partners, the careers of our employees and the challenges facing our society and environment. More than 50,000 employees in 30 countries are already working on innovative solutions in various engineering and IT sectors such as aerospace, renewable energy, medical technology, railway technology and automotive. Job Description YOU⦠verify mixed-signal designs on block and system level resting upon formal and functional verification interpret product requirements to create the verification concept and the product verification specification perform random-constraint testbenches according to the state of the art create assertions to prove the design using formal methods work in collaboration with lab and test engineers, designers, system architects, and verification engineers across multiple sites Qualifications YOU⦠have completed engineering degree in electrical engineering, computer science or similar studies already have practical experience in the field of digital functional verification and common safety standards have extensive programming skills in coding in System Verilog and System Verilog assertions have good knowledge of UVM methodology, scripting languages like Python or Perl and ability to interpret RTL and Gatelevel code have good communication skills in English We value diversity and therefore welcome all applications - regardless of gender, nationality, ethnic and social origin, religion/belief, disability, age and sexual orientation and identity. Severely disabled persons will be given preferential consideration if they are equally qualified. Do you have any questions?
Then contact me: Γzlem Mumin (Tel.: +49 89 255552-331) Or apply now using our online application form. Additional Information Talent Management - we develop your career Work life balance - flexible working hours and mobile working possible Fit and relaxed β with EGYM Wellpass Enjoy biking β always on tour with bike leasing Green Mobility - with us you can travel at a reduced rate ...in addition we offer a permanent employment contract, corporate benefits and team events.
Contract Type: Permanent
Region: Bayern