Role & seniority: Post-Silicon ASIC Validation Engineer; levels range from Sr. Engineer to Principal Engineer.

Stack/tools: Networking ASICs and chiplet-based SoCs; UCIe, PCIe, SerDes, Ethernet PHYs; Python for automation; lab equipment (oscilloscopes, BERTs, logic analyzers, JTAG); validation platforms, sockets, characterization boards; potential emulation/FPGA prototyping.

Top 3 responsibilities

Lead post-silicon validation and bring-up of networking ASICs and multi-die chiplet platforms.
Own validation planning, coverage, and test execution across UCIe, SerDes, and networking subsystems.
Develop automation/test infrastructure for high-speed link/protocol validation; perform silicon bring-up and cross-domain debugging.

Must-have skills

B.S. or M.S. in Electrical/Computer Engineering or related field.
Hands-on post-silicon validation and bring-up of complex ASICs/SoCs.
Proficiency with UCIe, PCIe, and high-speed interconnects; Python scripting; lab proficiency with oscilloscopes, BERTs, logic analyzers, JTAG.
Strong cross-functional communication.

Nice-to-haves

Experience with chiplet-based systems, UCIe protocol stack validation, multi-die integration (power, timing, thermal).
Familiarity with emulation/FPGA pre-silicon validation; hardware/software co-validation for networking protocols.
Knowledge of package-level interactions and signal integrity for high-speed interfaces.
Location & work type: Location not specified;

Full Description

Position Overview We are hiring multiple positions from Sr. Engineer to Principal Engineer.

We are looking for a highly experienced Post-Silicon ASIC Validation Engineer with deep expertise in networking ASICs and chiplet-based architectures. You will lead bring-up, validation, and characterization of complex multi-die systems integrating high-speed interconnects such as UCIe, SerDes, PCIe, and Ethernet PHYs. This position offers the opportunity to work on next-generation networking SoCs and disaggregated chiplet platforms, collaborating across architecture, design, firmware, and system teams to ensure first-silicon success and robust product readiness. Responsibilities Drive post-silicon validation and bring-up of networking ASICs and chiplet-based SoCs. Own validation planning, coverage definition, and test execution across UCIe, SerDes, and networking subsystems. Develop automation and test infrastructure for high-speed link and protocol validation (Python). Perform silicon bring-up, including power sequencing, link training, and PHY initialization. Execute link-level and system-level validation of UCIe interfaces, die-to-die interconnects, and high-bandwidth chiplet fabrics. Debug complex cross-domain issues spanning RTL, firmware, analog PHY, and package-level interactions. Characterize signal integrity, latency, throughput, and thermal/power behavior across PVT corners. Collaborate with board design and test engineering teams on validation platforms, sockets, and characterization boards. Qualifications

B. S. or M.S. in Electrical Engineering, Computer Engineering, or related field.

Experience in post-silicon validation and bring-up of complex ASICs or SoCs.
Hands-on experience with UCIe, PCIe and high-speed interconnect standards.
Proficiency in Python for scripting, automation, and data analysis.
Strong lab experience using oscilloscopes, BERTs, logic analyzers, and JTAG-based debuggers.
Excellent communication skills and experience working in cross-functional silicon development teams.
Preferred Qualifications
Experience with chiplet-based systems, UCIe protocol stack validation, and multi-die integration challenges (power delivery, timing, thermal).
Familiarity with emulation or FPGA prototyping platforms for pre-silicon validation.
Exposure to hardware/software co-validation for networking protocols or control-plane software.
Strong knowledge of package-level interactions and signal integrity analysis for high-speed interfaces.

Why Join Us? At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.