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Google • Fremont, California, United States
Salary: $183,000 - $271,000 / year
Role & seniority: Senior/Staff Custom Silicon Engineer (bring-up lead, verification-focused)
Stack/tools: Verilog/SystemVerilog; hardware design in HDL; EDA tools for circuit design/analysis; Automated Test Equipment (ATE); FPGA-based platforms; DFT techniques (hierarchical DFT, compression, diagnosis); test plan development and silicon validation workflows
Lead bring-up and debugging on silicon and FPGA-based platforms; analyze silicon failures with cross-team collaboration
Define and improve silicon validation flow, tooling, scripts to enhance efficiency and coverage
Architect, design, and implement digital logic; define test plans, assertions, and debug logic with verification team; ensure DFT plan integration with Architecture, Physical Design, and Test Engineering
Must-have skills: Bachelor’s degree in Electrical/Computer Engineering or CS (or equivalent); 8 years analog circuit design experience with simulation/verification; experience with EDA tools; proficiency in Verilog/SystemVerilog; strong problem-solving and collaboration abilities
Nice-to-haves: Master’s or PhD in EE/CE/CS with emphasis on computer architecture; 10+ years in custom silicon design (digital logic, analog, test, DFT); advanced DFT techniques (hierarchical DFT, compression, diagnosis); custom silicon bringup and in-depth silicon validation; excellent communication and teamwork
Location & work type: US-based, full-time position; on-sit
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in analog circuit design, including simulation and verification. Experience working with relevant electronic design automation (EDA) tools for circuit design and analysis.
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 10 years of experience in custom silicon design, with a focus on digital logic design, analog design and test, and DFT implementation. Experience with advanced DFT techniques such as hierarchical DFT, compression, and diagnosis. Experience with custom silicon bringup, leading test plan development, and performing in-depth silicon validation. Proficiency in hardware description languages (e.g., Verilog, SystemVerilog). Excellent problem-solving, communication, and teamwork abilities.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will lead custom silicon bringup, Verilog code development, and Automated Test Equipment (ATE) engineering. You will be responsible for defining post-silicon validation specifications and executing in-depth debug, specifically focusing on microdisplay backplane validation.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.
The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
Lead the bring-up process on debugging stations, including, but not limited to, FPGA-based platforms. Additionally, assist in the analysis of silicon failures and collaborate with design and test engineering teams to ascertain root causes. Advocate enhancements in the silicon validation flow, encompassing new tools, methodologies, and scripts, to significantly boost efficiency and coverage. Forge partnerships with the Architecture, Physical Design, and Test Engineering teams to guarantee seamless integration and execution of the Design-for-Test (DFT) plan. Architect, design, and implement digital logic utilizing Verilog or System Verilog, deriving from high-level specifications. Collaborate with the verification team to meticulously define test plans, formulate assertions, and debug logic issues.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .