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Google • Fremont, California, United States
Salary: USD 183,000–271,000 per year
Role & seniority
Stack / tools
Verilog / SystemVerilog
Digital RTL design, emulation (FPGA/other platforms), silicon bring-up
EDA tools for synthesis, Static Timing Analysis (STA), and DFT
DFT techniques: hierarchical DFT, compression, diagnosis
RTL verification planning, debugging, and test-automation scripts
Top 3 responsibilities
Lead RTL verification and pre-silicon to post-silicon validation for CMOS backplane; manage bring-up on first silicon and debugging across platforms
Develop and implement design flows, tools, and scripts to improve validation efficiency and coverage; define test plans and assertions with verification team
Collaborate with architecture, physical design, and test engineering to ensure DFT integration and successful silicon validation
Must-have skills
8 years in analog circuit design (simulation/verification) and 10 years in ASIC/SoC design with digital logic and DFT
Proficiency in Verilog/SystemVerilog; strong RTL design and debugging capabilities
Experience with EDA tools for synthesis, STA, and DFT; hands-on emulation/validation workflows
Excellent problem-solving, investigative, communication, and teamwork abilities
Nice-to-haves
Advanced DFT techniques (hierarchical DFT, compression, diagnosis)
Experience leading cross-functional validation efforts and silicon bring-up
Prior exposure to display/AR or CMOS backplane contexts
Location & work type
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 8 years of experience in analog circuit design, including simulation and verification. Experience working with relevant Electronic Design Automation (EDA) tools for circuit design and analysis.
10 years of experience in Application-Specific Integrated Circuit/System on a Chip (ASIC/SoC) design, with a focus on both digital logic design and DFT implementation. Experience with industry-standard EDA tools for synthesis, Static Timing Analysis (STA) and DFT. Experience with advanced DFT techniques such as hierarchical DFT, compression, and diagnosis. Proficiency in hardware description languages (Verilog, SystemVerilog). Excellent problem-solving/investigative skills, communication and teamwork abilities.
About the jobWe are seeking a Lead Silicon Pre-to-Post Validation Engineer with experience in writing verilog code to join our team. In this dual-capacity role, you will be responsible for both the silicon emulation (pre silicon) to silicon validation of Complementary Metal–Oxide–Semiconductor (CMOS) backplane. You will also be responsible for post silicon validation specification and execution. This position requires an in-depth understanding of Register-transfer level (RTL) design, digital verification, and all aspects of micro display validation.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.
The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
Provide comprehensive support for RTL verification through the utilization of various emulation techniques and the development of corresponding design flows. Upon the arrival of first silicon, lead the bring-up process on various debugging stations, including, but not limited to, Field Programmable Gate Array (FPGA) based platforms. Assist in the analysis of silicon failures and collaborate with design and test engineering teams to ascertain root causes. Advocate enhancements in the validation flow, encompassing new tools, methodologies, and scripts, to boost efficiency and coverage. Forge partnerships with architecture, physical design, and test engineering teams to guarantee integration and execution of the Design-for-Test (DFT) plan. Architect, design, and implement digital logic utilizing verilog or system verilog, deriving from specifications. Work closely with the verification team to define test plans, formulate assertions, and debug logic issues, ensuring functional correctness.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .