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Apple • Texas, United States
Role & seniority: Design Verification (DV) Engineer; experienced DV professional (seniority implied as mid-to-senior).
Stack/tools: SystemVerilog, UVM; verification methodologies and tools (simulators, waveform viewers); verification environments with stimulus, checkers, assertions, trackers, and coverage; scripting (Python, Perl, TCL); C/C++; gate-level simulations; UPF/power-aware methods; experience with PCIe, USB, DDR; formal verification basics.
Establish DV methodology and develop scalable, portable verification environments; create verification plans aligned with IP micro-architecture.
Develop test-benches, stimulus, checkers, assertions, coverage infrastructure; write and debug tests; enable regression and feature bring-up.
Execute verification plans, debug test failures, track DV progress with metrics (bugs, coverage), and provide sign-off for RTL freeze and tape-out.
Deep knowledge of SystemVerilog and UVM; scalable/portable test-benches.
Proven experience with verification methodologies, simulators, and waveform viewers; automation and coverage collection.
C/C++ knowledge; G/L gate-level simulations; familiarity with PCIe or USB; basic formal verification concepts; scripting (Python, Perl, TCL).
UPF or other power-aware verification; experience with DDR; broader formal verification experience; some exposure to LLM-assisted efficiency/quality improvements.
Location
At Apple, we work to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but
not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
DESCRIPTION
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.
MINIMUM QUALIFICATIONS
Bachelor's degree required
PREFERRED QUALIFICATIONS
Deep knowledge of SystemVerilog and UVM Deep knowledge in developing scalable and portable test-benches Proven experience with verification methodologies and tools such as simulators, waveform viewers Build and run automation, coverage collection, gate level simulations Some UVM knowledge, C/C++ level knowledge Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR Basic knowledge of formal verification methodology Some experience with power-aware (UPF) or similar verification methodology Knowledge of one of the scripting languages such as Python, Perl, TCL Some working experience using LLMs for efficiency and quality