Full Description

#WeAreIn for jobs that impact everyone's life. Build the future nobody’s dreamed of yet... are you ready to rethink the impossible? As a Mixed Signal Verification Engineer on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?

Your Role

Key responsibilities in your new role

Contribute to verification in complex projects: understanding requirements, actively supporting the definition & review of the verification plan, setting up verification metrics in digital & mixed-signal environments, developing test cases and ensuring reportscompliance. Responsibilities involve coordinating verification activities for given projects. Apply methodologies (e.g. Universal Verification Methodology (UVM /UVM-AMS) and execute tests in these environments on RTL, gate-level, and mixed-signal designs Create reusable verification components and environments Closely cooperate with analogue and digital designers as well asconcept and verification engineers Identify deficiencies in verification methodology and simulation performance, and implement improvements Identify and address synergies between the Pre-Silicon Verification methodology and the Post-Silicon Validation This role is not just about verification; it’s about inspiring andmentoring junior verification engineers while providing invaluabletechnical support and guidance to development teams and business partners

In addition, you will

• Create new and improve existing verification environments
• Contribute to create a smooth x-domain verification & validationmethodology
• Actively participate in Infineon verification communities
• Provide technical guidance/assistance when needed in the projectsrelated to interaction topic

Your Profile

Qualifications and skills to help you succeed

A degree in Electronics Engineering or similar field of studies with specific knowledge in semiconductor development At least 5 years of pre-silicon verification experience using UVM methodology Demonstrates technical proficiency with state-of-the-art verification methodologies and tool flows Act as a technical lead through exploring new environments and identifying potential enhancement areas through new methodology Good knowledge of VHDL, Verilog, C, C++, SystemVerilog Self-motivated, flexible, good communication with interpersonal skills and is a good team player who can work well with both internal andexternal partners Candidate has proven ability to achieve results in a very dynamic,multi-site environment and be able to coordinate with priorities and self-initiatives Demonstrated innovation drive Ability to improve efficiency through scripting and automation Strong stakeholders management across multiple groups & sites Fluent English communication is mandatory