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Synopsys Inc • Ottawa, Ontario, Canada
Role & seniority: Experienced Verification Engineer (8+ years in digital verification)
Stack/tools: SystemVerilog, UVM, Verilog/VHDL, scripting languages, C/C++, coverage-driven verification
Define and build verification environments for IP-level designs using SystemVerilog and UVM
Develop test cases, checkers, and coverage metrics; apply advanced verification techniques (SerDes)
Provide technical leadership, mentor junior engineers, and drive end-to-end verification and process improvements
8+ years in digital verification
Expertise in SystemVerilog, Verilog/VHDL, and UVM
Coverage-driven RTL verification; strong scripting and C/C++ skills
Ability to define verification plans and develop testbenches
Mentoring/leadership experience
Cross-functional collaboration across global teams
SerDes-specific verification exposure
Location & work type: Location not specified; work type not specified
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You are an experienced verification engineer with at least 8 years in digital verification. You thrive in collaborative environments, enjoy mentoring others, and have a passion for solving complex technical challenges. You’re skilled in System Verilog, UVM, scripting, and bring a creative, systematic approach to problem-solving. Your strong communication skills and proactive mindset make you a valuable team player eager to deliver high-quality results.
Define and build verification environments for IP-level designs using System Verilog and UVM. Apply advanced verification techniques for SerDes applications. Develop test cases, checkers, and coverage metrics. Provide technical leadership and mentor junior engineers. Collaborate with cross-functional teams globally. Drive end-to-end verification and continuous process improvement.
Ensure robust digital design verification and high product quality. Influence new product architectures and development strategies. Mentor and grow the engineering team. Accelerate project delivery by resolving verification challenges early. Enhance Synopsys’ leadership in digital verification. Foster a culture of innovation and collaboration.
Bachelor’s or Master’s in Electrical/Computer Engineering or related field; 8+ years of digital verification experience. Expertise in System Verilog, Verilog, or VHDL and UVM. Experience with coverage-driven RTL verification. Strong scripting and C/C++ programming skills. Ability to define verification plans and develop testbenches.
Self-motivated, collaborative, and a strong communicator. Creative, analytical, and adaptable to new challenges.
Join a high-performing engineering team focused on digital verification of leading-edge IP, collaborating across domains and geographies to deliver innovative solutions.