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Synopsys Inc • Ottawa, Ontario, Canada
Role & seniority: Experienced verification architect; senior technical lead with mentoring responsibilities
Stack/tools: SystemVerilog, Verilog, VHDL, UVM; scripting/programming in Python, Perl, C/C++
Provide technical leadership and mentor junior engineers
Define/implement advanced verification plans and UVM-based testbenches
Drive verification process improvements and automate flows; collaborate with global cross-functional teams
12+ years in digital design/verification; strong SystemVerilog/Verilog/VHDL expertise
UVM with coverage-driven RTL verification; ability to architect testbenches and verification plans
Proficiency in Python, Perl, C/C++; experience with automation
Experience with 200G SerDes verification
Track record of first-silicon success and faster time-to-market; process-improvement mindset
Location & work type: Location and work-type not specified in the text; no explicit details provided
At Synopsys, we drive innovations that shape how we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. As leaders in chip design, verification, and IP integration, we empower the creation of high-performance silicon chips and software. Join us to transform the future through continuous innovation.
You are an experienced verification architect who thrives on technical leadership and mentoring others. You excel in digital design and verification, enjoy collaborating with global teams, and are motivated by delivering high-quality solutions. Your expertise includes System Verilog, Verilog, VHDL, UVM, and scripting/programming in C/C++. You’re proactive, inclusive, and passionate about process improvement and innovation. If you’re ready to make an impact and help shape the future of semiconductor technology, we’d love to meet you.
Provide technical leadership and mentor junior engineers. Collaborate with cross-functional, global teams. Define and implement advanced verification plans and methodologies. Develop and maintain UVM-based testbenches. Drive process improvements for verification efficiency. Automate verification flows using scripting and programming skills.
Ensure robust verification for complex ASIC and IP designs. Support first-silicon success and faster time-to-market. Elevate team skills and technical excellence. Champion best verification practices and tools. Enhance collaboration across global teams. Promote continuous improvement in verification processes.
BSEE or MSEE with at least 12+ years of direct industry experience in digital design verification with System Verilog, Verilog, or VHDL. Expertise in UVM and coverage-driven RTL verification. Proficiency in scripting and programming (Python, Perl, C/C++). Ability to define verification plans and architect testbenches. Experience with 200G SerDes verification is an asset.
Collaborative leader and effective communicator. Mentor who empowers others. Analytical, detail-oriented problem solver. Adaptable and innovative.
Join a diverse, world-class engineering team dedicated to delivering industry-leading verification solutions for next-generation semiconductor products.