Cookies & analytics consent
We serve candidates globally, so we only activate Google Tag Manager and other analytics after you opt in. This keeps us aligned with GDPR/UK DPA, ePrivacy, LGPD, and similar rules. Essential features still run without analytics cookies.
Read how we use data in our Privacy Policy and Terms of Service.
🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.

Sivaltech • San Francisco, California, United States
Role & seniority: Design Verification Engineer, senior-level (10+ years in verification)
Stack/tools: SystemVerilog, UVM, RTL verification; programming in C/C++, Perl; scripting
Develop verification environments using SystemVerilog and UVM
Design verification components and behavioral models
Implement coverage and assertions; debug simulation failures and analyze coverage results
Bachelor’s degree
10+ years in verification
Expertise in SystemVerilog, UVM, RTL verification methodologies
Strong C/C++, Perl, and scripting skills
Experience with emulators and FPGA-based prototyping
Knowledge of CPU, DDR, bus/protocol networks, or DSP design
Location & work type: California Bay Area, CA; work type not specified
Company Description Sivaltech is a leading design services company specializing in ASIC/FPGA, Analog, and Embedded Software with offices in California, USA, and Bangalore, India. Recognized as a trusted design services partner, Sivaltech collaborates with both Fortune 500 companies and innovative startups in the semiconductor industry. The company brings extensive experience across diverse domains including GPUs, CPUs, wireless, communications, medical, broadband, and consumer electronics. Sivaltech is committed to solving complex design challenges and delivering high-quality solutions to its clients.
Hi,
Hope you're doing well!
We're excited to share an opportunity with you for a Design Verification Engineer position with a leading supplier of state-of-the-art SoC and embedded IP in the California Bay Area. 🚀
Developing verification environments using System Verilog and UVM
Designing verification components and behavioral models
Implementing coverage and assertions
Debugging simulation failures and analyzing coverage results
Bachelor's degree
10+ years of industry experience in verification
Expertise in System Verilog, UVM, and RTL verification methodologies
Strong programming skills in C/C++, Perl, and scripting
Experience with Emulators and FPGA-based prototyping
Knowledge of CPU, DDR, Bus Protocol, Network Protocol, or DSP design
If you're interested in exploring this opportunity, please share your updated resume and availability for a discussion.